TPS7A8300 2-A, 6-µVRMS, RF, LDO Voltage Regulator
- SBVS197F May 2013 – October 2015 TPS7A8300
  
  PRODUCTION DATA.

Full reading width

DATA SHEET

TPS7A8300 2-A, 6-µVRMS, RF, LDO Voltage Regulator

1 Features

Ultralow Dropout: 125 mV Maximum at 2 A
Output Voltage Noise: 6 µV_RMS
Power-Supply Ripple Rejection:
- 40 dB at 1 MHz
Input Voltage Range:
- Without BIAS: 1.4 V to 6.5 V
- With BIAS: 1.1 V to 6.5 V
Two Output Voltage Modes:
- ANY-OUT™ Version (User-Programmable Output via PCB Layout):
  - No External Resistor Required
  - Output Voltage Range: 0.8 V to 3.95 V
- Adjustable Version:
  - Output Voltage Range: 0.8 V to 5.0 V
1.0% Accuracy Over Line, Load, and Temperature
Stable with a 22-µF Output Ceramic Capacitor
Programmable Soft-Start Output
Power-Good (PG) Output
Available Packages:
- 5-mm × 5-mm VQFN-20
- 3.5-mm × 3.5-mm VQFN-20

2 Applications

RF, IF Components: VCO, ADC, DAC, LVDS
Wireless Infrastructure: SerDes, FPGA, DSP™
Test and Measurement
Instrumentation, Medical, and Audio

Application Example

3 Description

The TPS7A8300 is a low-noise (6 µV_RMS), low-dropout voltage regulator (LDO) capable of sourcing a 2-A load with only 125 mV of maximum dropout.

The TPS7A8300 output voltages are fully user-adjustable (up to 3.95 V) using a printed circuit board (PCB) layout without the need of external resistors, thus reducing overall component count. For higher output voltage applications, the device achieves output voltages up to 5 V with the use of external resistors. The device supports very low input voltages (down to 1.1 V) with the use of an additional BIAS rail.

With very high accuracy (1% over line, load, and temperature), remote sensing, and soft-start capabilities to reduce inrush current, the TPS7A8300 is ideal for powering high-current, low-voltage devices such as high-end microprocessors and field-programmable gate arrays (FPGAs).

The TPS7A8300 is designed to power-up noise-sensitive components in high-speed communication applications. The very low-noise, 6-µV_RMS device output and high broad-bandwidth PSRR (40 dB at
1 MHz) minimizes phase noise and clock jitter in high-frequency signals. These features maximize performance of clocking devices, analog-to-digital converters (ADCs), and digital-to-analog converters (DACs).

For applications where positive and negative low-noise rails are required, consider TI's TPS7A33 family of negative high-voltage, ultralow-noise linear regulators.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS7A8300	VQFN (20)	5.00 mm × 5.00 mm
TPS7A8300	VQFN (20)	3.50 mm × 3.50 mm

For all available packages, see the orderable addendum at the end of the datasheet.

4 Revision History

Changes from E Revision (August 2014) to F Revision

Added title to page 1 graphic Go
Updated ESD Ratings table to current standards Go
Changed Figure 52: changed connection of EN pin Go
Changed Enable (EN) and Undervoltage Lockout (UVLO) section: updated wording for better clarity on use of the Enable (EN) pin Go

Changes from D Revision (February 2013) to E Revision

Changed format to meet latest data sheet standards; added new sections, and moved existing sectionsGo
Changed first ANY-OUT sub-bullet of fifth Features bullet Go
Changed eighth Features bullet: broke Soft-Start Output and PG Output into two separate Features bullets Go
Changed first sentence of second paragraph in Description section Go
Changed RGW and RGR drawings: removed spacing between number and unit in pins 5 to 7 and 9 to 11 Go
Changed first row of Pin Functions table: deleted spacing between number and unit in pin namesGo
Added capacitor value to BIAS pin description in Pin Functions tableGo
Changed 87% to 89% in the PG pin description of the Pin Functions tableGo
Changed thermal pad description in Pin Functions tableGo
Changed conditions statements for Absolute Maximum Ratings and Recommended Operating Conditions tables Go
Added Recommended Operating Conditions tableGo
Changed the Typical Characteristics section: changed all curve titles and conditions Go
Changed title of Figure 11 Go
Added Overview section Go
Changed second paragraph of Overview section: changed that can be groups, as follows to including Go
Changed functional block diagram footnoteGo
Added Feature Description sectionGo
Changed adjustable version to adjustable configuration in first paragraph of Adjustable Operation section Go
Changed Figure 51: removed right-hand side diagramGo
Added Figure 52 Go
Changed second sentence in Internal Charge Pump section Go
Changed last sentence of UVLO sectionGo
Changed oscillates to cycles in first paragraph of Thermal Protection sectionGo
Changed first sentence of Programmable Soft-Start sectionGo
Added Device Functional Modes sectionGo
Added Application Information section Go
Changed second paragraph of Noise sectionGo
Added Typical Application section Go
Added Figure 57 Go

Changes from C Revision (July 2013) to D Revision

Changed document status from Mixed to Production DataGo
Deleted footnote from second sub-bullet of last Features bulletGo
Deleted footnote from RGR package drawingGo
Changed GND pin description in Pin Descriptions tableGo

Changes from B Revision (July 2013) to C Revision

Deleted PG Functionality sectionGo
Changed Power-Good sectionGo
Changed text in Feed-Forward Capacitor subsectionGo

Changes from A Revision (June 2013) to B Revision

Changed from product preview to production data (mixed status)Go

Changes from * Revision (May 2013) to A Revision

Changed product preview data sheetGo

5 Pin Configurations and Functions

RGW Package

5-mm × 5-mm VQFN-20

Top View

RGR Package

3.5-mm × 3.5-mm VQFN-20

Top View

Pin Functions

PIN			DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
50mV, 100mV, 200mV, 400mV, 800mV, 1.6V	5, 6, 7, 9, 10, 11	I	Output voltage setting pins. Connect these pins to ground or leave floating. Connecting these pins to ground increases the output voltage by the value of the pin name; multiple pins can be simultaneously connected to GND to select the desired output voltage. Leave these pins floating (open) when not in use. See the ANY-OUT Programmable Output Voltage section for more details.
BIAS	12	I	BIAS supply voltage pin for the use of 1.1 V ≤ V_IN ≤ 1.4 V and to connect a 10-µF capacitor between this pin and ground.
EN	14	I	Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. See the Start-Up section for more details.
FB	3	I	Output voltage feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from FB to OUT (as close to the device as possible) is recommended for low-noise applications to maximize ac performance. The use of a feed-forward capacitor may disrupt PG (power good) functionality. See the ANY-OUT Programmable Output Voltage and Adjustable Operation sections for more details.
GND	8, 18	—	Ground pin. These pins must be externally shorted for the RGR package option.
IN	15-17	I	Input supply voltage pin. A 10-μF input ceramic capacitor is required. See the Input and Output Capacitor Requirements (CIN and COUT) section for more details.
OUT	1, 19, 20	O	Regulated output pin. A 22-μF or larger ceramic capacitor is required for stability (a 10-μF minimum effective capacitance is required). See the Input and Output Capacitor Requirements (CIN and COUT) section for more details.
PG	4	O	Active-high power-good pin. An open-drain output indicates when the output voltage reaches 89% of the target. The use of a feed-forward capacitor may disrupt PG (power good) functionality. See the Power-Good Function section for more details.
SNS	2	I	Output voltage sense input pin. Connect this pin only if the ANY-OUT feature is used. See the ANY-OUT Programmable Output Voltage and Adjustable Operation sections for more details.
NR/SS	13	—	Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces reference voltage noise and also enables the soft-start function. Although not required, a capacitor is recommended for low-noise applications to connect a 10-nF capacitor from NR/SS to GND (as close to the device as possible) to maximize ac performance. See the Noise-Reduction and Soft-Start Capacitor (CNR/SS) section for more details.
Thermal Pad	Pad	—	Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

6 Specifications

6.1 Absolute Maximum Ratings

over junction temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Voltage	IN, BIAS, PG, EN	–0.3	7.0	V
	IN, BIAS, PG, EN (5% duty cycle)	–0.3	7.5
	SNS, OUT	–0.3	V_IN + 0.3 ⁽²⁾
	NR/SS, FB	–0.3	3.6
	50mV, 100mV, 200mV, 400mV, 800mV, 1.6V	–0.3	V_OUT + 0.3
Current	OUT	Internally limited		A
Current	PG (sink current into device)		5	mA
Operating junction temperature, T_J		–55	150	°C
Storage temperature, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The absolute maximum rating is V_IN + 0.3 V or 7.0 V, whichever is smaller.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over junction temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Input supply voltage range	1.1	6.5	V
V_BIAS	Bias supply voltage range⁽¹⁾	3.0	6.5	V
I_OUT	Output current	0	2	A
T_J	Operating junction temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS7A8300		UNIT
		RGW (QFN)	RGR (QFN)
		20 PINS	20 PINS
R_θJA	Junction-to-ambient thermal resistance	33.6	35.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	30.0	47.6	°C/W
R_θJB	Junction-to-board thermal resistance	14.0	12.3	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	0.5	°C/W
ψ_JB	Junction-to-board characterization parameter	14.0	12.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.6	1.0	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over operating temperature range (T_J = –40°C to 125°C), {1.1 V ≤ V_IN < 1.4 V and 3.0 V ≤ V_BIAS ≤ 6.5 V} or {V_IN ≥ 1.4 V and V_BIAS open}⁽¹⁾, V_IN ≥ V_OUT(TARGET) + 0.3 V⁽²⁾, V_OUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND⁽³⁾, V_EN = 1.1 V, C_OUT =
22 μF, C_NR/SS = 0 nF, C_FF = 0 nF, and PG pin pulled up to V_IN with 100 kΩ, unless otherwise noted.
Typical values are at T_J = 25°C.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IN	Input supply voltage range		1.1		6.5	V
V_BIAS	Bias supply voltage range⁽¹⁾		3.0		6.5	V
V_(REF)	Reference voltage	V_(REF) = V_(FB) = V_(NR/SS)		0.8		V
V_UVLO1(IN)	Input supply UVLO with BIAS	V_IN increasing		1.02	1.085	V
V_HYS1(IN)	V_UVLO1(IN) hysteresis			320		mV
V_UVLO2(IN)	Input supply UVLO without BIAS	V_IN increasing		1.31	1.39	V
V_HYS2(IN)	V_UVLO2(IN) hysteresis			253		mV
V_UVLO(BIAS)	Bias supply UVLO	V_BIAS increasing		2.83	2.9	V
V_HYS(BIAS)	V_UVLO(BIAS) hysteresis			290		mV
V_OUT	Output voltage range	Using voltage setting pins (50mV, 100mV, 200mV, 400mV, 800mV, and 1.6V)	0.8 – 1.0%		3.95 + 1.0%	V
	Output voltage range	Using external resistors	0.8 – 1.0%		5.0 + 1.0%	V
	Output voltage accuracy⁽⁴⁾⁽⁵⁾	0.8 V ≤ V_OUT ≤ 5 V, 5 mA ≤ I_OUT ≤ 2 A	–1.0%		1.0%
	Output voltage accuracy⁽⁴⁾⁽⁵⁾	V_IN = 1.5 V, V_OUT = 1.2 V, 5 mA ≤ I_OUT ≤ 1.2 A	–1.0%		1.0%
ΔV_O(ΔVI)	Line regulation	I_OUT = 5 mA, 1.4 V ≤ V_IN ≤ 6.5 V		0.003		%/V
ΔV_O(ΔIO)	Load regulation	5 mA ≤ I_OUT ≤ 2 A		0.0001		%/A
V_(DO)	Dropout voltage	V_IN ≥ 1.4 V and V_BIAS open, 0.8 V ≤ V_OUT ≤ 5.0 V, I_OUT = 2 A, V_FB = 0.8 V – 3%			200	mV
V_(DO)	Dropout voltage	V_IN = 1.1 V, V_BIAS = 5.0 V, V_OUT(TARGET) = 0.8 V, I_OUT = 2 A, V_FB = 0.8 V – 3%			125	mV
I_(LIM)	Output current limit	V_OUT forced at 0.9 × V_OUT(TARGET), V_IN = V_OUT(TARGET) + 300 mV	2.1	3.4	4.2	A
I_(GND)	GND pin current	Minimum load, V_IN = 6.5 V, no V_BIAS supply, I_OUT = 5 mA		2.8	4	mA
		Maximum load, V_IN = 1.4 V, no V_BIAS supply, I_OUT = 2 A		3.7	5	mA
		Shutdown, PG = (open), V_IN = 6.5 V, no V_BIAS supply, V_(EN) = 0.5 V			2.5	μA
I_(EN)	EN pin current	V_IN = 6.5 V, no V_BIAS supply, V_(EN) = 0 V and 6.5 V	–0.1		0.1	μA
I_(BIAS)	BIAS pin current	V_IN = 1.1 V, V_BIAS = 6.5 V, V_OUT(TARGET) = 0.8 V, I_OUT = 2 A		2.3	3.5	mA
V_IL(EN)	EN pin low-level input voltage (disable device)		0		0.5	V
V_IH(EN)	EN pin high-level input voltage (enable device)		1.1		6.5	V
V_IT(PG)	PG pin threshold	For the direction PG↓ with decreasing V_OUT	0.82 V_OUT	0.872 V_OUT	0.93 V_OUT	V
V_hys(PG)	PG pin hysteresis	For PG↑		0.02 V_OUT		V
V_OL(PG)	PG pin low-level output voltage	V_OUT < V_IT(PG), I_PG = –1 mA (current into device)			0.4	V
I_lkg(PG)	PG pin leakage current	V_OUT > V_IT(PG), V_(PG) = 6.5 V			1	μA
I_(NR/SS)	NR/SS pin charging current	V_NR/SS = GND, V_IN = 6.5 V	4.0	6.2	9.0	μA
I_FB	FB pin leakage current	V_IN = 6.5 V	–100		100	nA
PSRR	Power-supply ripple rejection	f = 1 MHz, V_IN = 3.8 V, V_OUT = 3.3 V, I_OUT = 2 A, C_NR/SS = 10 nF, C_FF = 10 nF		40		dB
V_n	Output noise voltage	BW = 10 Hz to 100 kHz, V_IN = 1.4 V, V_OUT = 0.8 V, I_OUT = 1.5 A, C_NR/SS = 10 nF, C_FF = 10 nF		6		μV_RMS
T_sd	Thermal shutdown temperature	Shutdown, temperature increasing		160		°C
T_sd	Thermal shutdown temperature	Reset, temperature decreasing		140		°C
T_J	Operating junction temperature		–40		125	°C

(1) BIAS supply is required when the V_IN supply is below 1.4 V. Conversely, no BIAS supply is needed when the V_IN supply is higher than or equal to 1.4 V.

(2) V_OUT(TARGET) is the calculated V_OUT target value from the output voltage setting pins: 50mV, 100mV, 200mV, 400mV, 800mV, and 1.6V in a fixed configuration. In an adjustable configuration, V_OUT(TARGET) is the expected V_OUT value set by the external feedback resistors.

(3) This 50-Ω load is disconnected when the test conditions specify an I_OUT value.

(4) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.

(5) The device is not tested under conditions where V_IN > V_OUT + 2.5 V and I_OUT = 2 A, because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test.

6.6 Typical Characteristics

At T_J = 25°C, {1.1 V ≤ V_IN < 1.4 V and 3.0 V ≤ V_BIAS ≤ 6.5 V} or {V_IN ≥ 1.4 V and V_BIAS open}

(1) BIAS supply is required when the V_IN supply is below 1.4 V. Conversely, no BIAS supply is needed when the V_IN supply is higher than or equal to 1.4 V.

, V_IN ≥ V_OUT(TARGET) + 0.3 V, V_OUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND, V_EN = 1.1 V, C_OUT = 22 μF, C_NR/SS = 0 nF, C_FF = 10 nF, and PG pin pulled up to V_IN with 100 kΩ, unless otherwise noted.

V_OUT(TARGET) = 0.8 V, I_OUT = 5 mA, V_BIAS = Open

Figure 1. Minimum ANY-OUT V_OUT Line Regulation

V_OUT(TARGET) = 0.8 V, V_IN = 1.4 V, V_BIAS = Open

Figure 3. Minimum ANY-OUT V_OUT, Minimum V_IN,
No BIAS Load Regulation

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V, I_OUT = 5 mA

Figure 5. Minimum ANY-OUT V_OUT, Minimum V_IN BIAS
Line Regulation

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V, V_BIAS = 6.5 V

Figure 7. Minimum Adjustable V_OUT, Minimum V_IN,
Maximum BIAS Load Regulation

V_OUT(TARGET) = 5 V, I_OUT = 5 mA, V_BIAS = Open

Figure 9. Maximum Adjustable V_OUT, No BIAS
Line Regulation

V_OUT(TARGET) = 5 V, V_IN = 5.3 V, V_BIAS = Open

Figure 11. Maximum Adjustable V_OUT Load Regulation

V_IN = 5.5 V, ANY-OUT, V_BIAS = Open,

Figure 13. Dropout Voltage vs Output Current

V_BIAS = Open, I_OUT = 2 A, ANY-OUT

Figure 15. Dropout Voltage vs Input Voltage

V_IN = 1.1 V, ANY-OUT, I_OUT = 2 A

Figure 17. Minimum V_IN Dropout Voltage vs Bias Voltage

V_OUT(TARGET) = 0.8 V, I_OUT = 5 mA, V_IN = 1.1 V

Figure 19. Minimum ANY-OUT V_OUT, Minimum V_IN
Quiescent Current vs Bias Voltage

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V, V_BIAS = 3 V

Figure 21. Minimum ANY-OUT V_OUT, V_IN, and BIAS
Quiescent Current vs Output Current

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V

Figure 23. Minimum ANY-OUT V_OUT, Minimum V_IN
Shutdown Current vs Bias Voltage

V_IN = 1.8 V, ANY-OUT, V_BIAS = Open, V_OUT(TARGET) = 1.5 V

Figure 25. Current Limit vs Output Voltage

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V, V_BIAS = 3 V

Figure 27. Minimum ANY-OUT V_OUT, V_IN, and BIAS
Current Limit vs Output Voltage

V_OUT(TARGET) = 0.8 V, V_BIAS = 3.0 V

Figure 29. Minimum ANY-OUT V_OUT, Minimum BIAS
Input UVLO Threshold vs Temperature

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V

Figure 31. Minimum ANY-OUT V_OUT, Minimum V_IN BIAS
UVLO Threshold vs Temperature

V_OUT(TARGET) = 0.8 V, V_IN = 6.5 V, V_BIAS = Open

Figure 33. Minimum ANY-OUT V_OUT, Maximum V_IN
Enable Threshold vs Temperature

V_IN = 6.5 V, V_OUT(TARGET) = 0.8 V, V_BIAS = Open

Figure 35. Minimum ANY-OUT V_OUT, Maximum V_IN, No BIAS PG Low Voltage vs PG Current

V_OUT(TARGET) = 0.8 V, V_IN = 6.5 V, V_BIAS = Open

Figure 37. Minimum ANY-OUT V_OUT, Maximum V_IN
PG Threshold vs Temperature

V_OUT(TARGET) = 0.8 V, V_IN = V_PG = 6.5 V, V_BIAS = Open

Figure 39. Minimum ANY-OUT V_OUT, Maximum V_IN
PG Current vs Temperature

V_OUT(TARGET) = 3.3 V, ANY-OUT, V_IN = V_EN = 3.8 V, V_BIAS = Open, I_OUT = 1.5 A, C_OUT = 22 µF, C_FF = 10 nF

Figure 41. Power-Supply Rejection vs C_NR/SS

V_IN = V_OUT(TARGET) + 0.5 V, ANY-OUT, V_BIAS = Open,
I_OUT = 1.5 A, C_OUT = 22 µF, C_NR/SS = C_FF = 10 nF

Figure 43. Spectral Noise Density vs Output Voltage

V_IN = 3.8 V, V_OUT(TARGET) = 3.3 V, ANY-OUT, V_BIAS = Open,
I_OUT = 1.5 A, C_OUT = 22 µF, C_NR/SS = 10 nF

Figure 45. Spectral Noise Density vs C_FF

V_IN = 1.4 V, V_OUT = 0.8 V, C_NR/SS = 0 nF

Figure 47. Start-Up (C_NR/SS = 0 nF)

V_IN = 1.4 V to 6 V to 1.4 V at 1 V/µs,
V_OUT = 0.8 V, I_OUT = 2 A, C_NR/SS = C_FF = 10 nF

Figure 49. Line Transient

V_OUT(TARGET) = 3.95 V, I_OUT = 5 mA, V_BIAS = Open

Figure 2. Maximum ANY-OUT V_OUT Line Regulation

V_OUT(TARGET) = 3.95 V, V_IN = 4.25 V, V_BIAS = Open

Figure 4. Maximum ANY-OUT V_OUT Load Regulation

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V, V_BIAS = 3 V

Figure 6. Minimum ANY-OUT V_OUT, V_IN, and
BIAS Load Regulation

V_OUT(TARGET) = 0.8 V, I_OUT = 5 mA, V_BIAS = Open

Figure 8. Minimum Adjustable V_OUT, No BIAS
Line Regulation

V_OUT(TARGET) = 0.8 V, V_IN = 1.4 V, V_BIAS = Open

Figure 10. Minimum Adjustable V_OUT, Minimum V_IN,
No BIAS Load Regulation

V_IN = 1.4 V, ANY-OUT, V_BIAS = Open, No BIAS

Figure 12. Minimum V_IN Dropout Voltage vs Output Current

V_BIAS = Open, I_OUT = 0.5 A, ANY-OUT

Figure 14. Dropout Voltage vs Input Voltage

V_IN = 1.1 V, ANY-OUT, I_OUT = 0.5 A

Figure 16. Dropout Voltage vs Bias Voltage

V_OUT(TARGET) = 0.8 V, I_OUT = 5 mA, V_BIAS = Open

Figure 18. Minimum ANY-OUT V_OUT, No BIAS
Quiescent Current vs Input Voltage

V_OUT(TARGET) = 0.8 V, V_IN = 1.4 V, V_BIAS = Open

Figure 20. Minimum ANY-OUT V_OUT, Minimum V_IN, No BIAS Quiescent Current vs Output Current

V_OUT(TARGET) = 0.8 V, V_BIAS = Open

Figure 22. Minimum ANY-OUT V_OUT, No BIAS
Shutdown Current vs Input Voltage

V_OUT(TARGET) = 0.8 V, V_BIAS = Open

Figure 24. Minimum ANY-OUT V_OUT, No BIAS
Soft-Start Current vs Input Voltage

V_OUT(TARGET) = 3.95 V, V_IN = 4.25 V, V_BIAS = Open

Figure 26. Maximum ANY-OUT V_OUT
Current Limit vs Output Voltage

V_OUT(TARGET) = 0.8 V, V_IN = 1.1 V, V_BIAS = 6.5 V

Figure 28. Minimum ANY-OUT V_OUT, Minimum V_IN,
Maximum BIAS Current Limit vs Output Voltage

V_OUT(TARGET) = 0.8 V, V_BIAS = Open

Figure 30. Minimum ANY-OUT V_OUT, No BIAS
Input UVLO Threshold vs Temperature

V_OUT(TARGET) = 0.8 V, V_IN = 1.4 V, V_BIAS = Open

Figure 32. Minimum ANY-OUT V_OUT, Minimum V_IN, No BIAS Enable Threshold vs Temperature

V_OUT(TARGET) = 0.8 V, V_IN = V_EN = 6.5 V, V_BIAS = Open

Figure 34. Minimum ANY-OUT V_OUT, Maximum V_IN
Enable Current vs Temperature

V_OUT(TARGET) = 0.8 V, V_IN = 1.4 V, V_BIAS = Open

Figure 36. Minimum ANY-OUT V_OUT, Minimum V_IN, No BIAS PG Low Voltage vs PG Current

V_OUT(TARGET) = 0.8 V, V_IN = 1.4 V, V_BIAS = Open

Figure 38. Minimum ANY-OUT V_OUT, Maximum V_IN, No BIAS PG Threshold vs Temperature

V_OUT(TARGET) = 3.3 V, ANY-OUT, V_IN = V_EN = 3.8 V, V_BIAS = Open, C_OUT = 22 µF, C_NR/SS = C_FF = 10 nF

Figure 40. Power-Supply Rejection vs Output Current

V_OUT(TARGET) = 1.2 V, ANY-OUT, V_BIAS = Open, I_OUT = 1.5 A, C_OUT = 22 µF, C_NR/SS = C_FF = 10 nF

Figure 42. Power-Supply Rejection vs Input Voltage

V_IN = 3.8 V, V_OUT(TARGET) = 3.3 V, ANY-OUT, V_BIAS = Open,
I_OUT = 1.5 A, C_OUT = 22 µF, C_FF = 10 nF

Figure 44. Spectral Noise Density vs C_NR/SS

V_IN = 3.85 V, V_OUT = 3.3 V, I_OUT = 100 mA to 1 A to 100 mA at 1 A/µs, C_O = 22 µF

Figure 46. Load Transient Response

V_IN = 1.4 V, V_OUT = 0.8 V, C_NR/SS = 10 nF

Figure 48. Start-Up

7 Detailed Description

7.1 Overview

The TPS7A8300 is a low-noise, high PSRR, low-dropout regulator capable of sourcing a 2-A load with only
125 mV of maximum dropout. The TPS7A8300 can operate down to 1.1-V input voltage and 0.8-V output voltage. This combination of low noise, high PSRR, and low output voltage makes the device an ideal low dropout (LDO) regulator to power a multitude of loads from noise-sensitive communication components in high-speed communication applications to high-end microprocessors or field-programmable gate arrays (FPGAs).

The TPS7A8300 block diagram contains several features, including:

A 2-A, low-dropout regulator with an internal charge pump,
Low-noise, 0.8-V reference,
Internal protection circuitry, such as undervoltage lockout (UVLO), foldback current limit, and thermal shutdown,
Programmable soft-start,
Power-good output, and
An integrated resistance network (ANY-OUT) with a 50-mV minimum resolution.

7.2 Functional Block Diagram

NOTE: 32R = 193.6 kΩ (that is, 1R = 6.05 kΩ).

7.3 Feature Description

7.3.1 ANY-OUT Programmable Output Voltage

The TPS7A8300 does not require external resistors to set output voltage, which is typical of adjustable low-dropout voltage regulators (LDOs). However, the TPS7A8300 uses pins 5, 6, 7, 9, 10, and 11 to program the regulated output voltage. Each pin is either connected to ground (active) or left open (floating). ANY-OUT programming is set by Equation 1 as the sum of the internal reference voltage (V_REF = 0.8 V) plus the accumulated sum of the respective voltages assigned to each active pin; that is, 50mV (pin 5), 100mV (pin 6), 200mV (pin 7), 400mV (pin 9), 800mV (pin 10), or 1.6V (pin 11). Table 1 summarizes these voltage values associated with each active pin setting for reference. By leaving all program pins open, or floating, the output is thereby programmed to the minimum possible output voltage equal to V_REF.

Equation 1. TPS7A8300 q_vout_anyout_bvs204.gif

Table 1. ANY-OUT Programmable Output Voltage

ANY-OUT PROGRAM PINS (Active Low)	ADDITIVE OUTPUT VOLTAGE LEVEL
Pin 5 (50mV)	50 mV
Pin 6 (100mV)	100 mV
Pin 7 (200mV)	200 mV
Pin 9 (400mV)	400 mV
Pin 10 (800mV)	800 mV
Pin 11 (1.6V)	1.6 V

Table 2 provides a full list of target output voltages and corresponding pin settings. The voltage setting pins have a binary weight; therefore, the output voltage can be programmed to any value from 0.8 V to 3.95 V in 50-mV steps.

There are several alternative ways to set the output voltage. The program pins can be driven using external general-purpose input/output pins (GPIOs), manually connected to ground using 0-Ω resistors (or left open), or hardwired by the given layout of the printed circuit board (PCB) to set the ANY-OUT voltage.

NOTE

For output voltages greater than 3.95 V, use a traditional adjustable configuration (see the Adjustable Operation section).

Table 2. User-Configurable Output Voltage Settings

V_OUT(TARGET) (V)	50mV	100mV	200mV	400mV	800mV	1.6V	V_OUT(TARGET) (V)	50mV	100mV	200mV	400mV	800mV	1.6V
0.80	Open	Open	Open	Open	Open	Open	2.40	Open	Open	Open	Open	Open	GND
0.85	GND	Open	Open	Open	Open	Open	2.45	GND	Open	Open	Open	Open	GND
0.90	Open	GND	Open	Open	Open	Open	2.50	Open	GND	Open	Open	Open	GND
0.95	GND	GND	Open	Open	Open	Open	2.55	GND	GND	Open	Open	Open	GND
1.00	Open	Open	GND	Open	Open	Open	2.60	Open	Open	GND	Open	Open	GND
1.05	GND	Open	GND	Open	Open	Open	2.65	GND	Open	GND	Open	Open	GND
1.10	Open	GND	GND	Open	Open	Open	2.70	Open	GND	GND	Open	Open	GND
1.15	GND	GND	GND	Open	Open	Open	2.75	GND	GND	GND	Open	Open	GND
1.20	Open	Open	Open	GND	Open	Open	2.80	Open	Open	Open	GND	Open	GND
1.25	GND	Open	Open	GND	Open	Open	2.85	GND	Open	Open	GND	Open	GND
1.30	Open	GND	Open	GND	Open	Open	2.90	Open	GND	Open	GND	Open	GND
1.35	GND	GND	Open	GND	Open	Open	2.95	GND	GND	Open	GND	Open	GND
1.40	Open	Open	GND	GND	Open	Open	3.00	Open	Open	GND	GND	Open	GND
1.45	GND	Open	GND	GND	Open	Open	3.05	GND	Open	GND	GND	Open	GND
1.50	Open	GND	GND	GND	Open	Open	3.10	Open	GND	GND	GND	Open	GND
1.55	GND	GND	GND	GND	Open	Open	3.15	GND	GND	GND	GND	Open	GND
1.60	Open	Open	Open	Open	GND	Open	3.20	Open	Open	Open	Open	GND	GND
1.65	GND	Open	Open	Open	GND	Open	3.25	GND	Open	Open	Open	GND	GND
1.70	Open	GND	Open	Open	GND	Open	3.30	Open	GND	Open	Open	GND	GND
1.75	GND	GND	Open	Open	GND	Open	3.35	GND	GND	Open	Open	GND	GND
1.80	Open	Open	GND	Open	GND	Open	3.40	Open	Open	GND	Open	GND	GND
1.85	GND	Open	GND	Open	GND	Open	3.45	GND	Open	GND	Open	GND	GND
1.90	Open	GND	GND	Open	GND	Open	3.50	Open	GND	GND	Open	GND	GND
1.95	GND	GND	GND	Open	GND	Open	3.55	GND	GND	GND	Open	GND	GND
2.00	Open	Open	Open	GND	GND	Open	3.60	Open	Open	Open	GND	GND	GND
2.05	GND	Open	Open	GND	GND	Open	3.65	GND	Open	Open	GND	GND	GND
2.10	Open	GND	Open	GND	GND	Open	3.70	Open	GND	Open	GND	GND	GND
2.15	GND	GND	Open	GND	GND	Open	3.75	GND	GND	Open	GND	GND	GND
2.20	Open	Open	GND	GND	GND	Open	3.80	Open	Open	GND	GND	GND	GND
2.25	GND	Open	GND	GND	GND	Open	3.85	GND	Open	GND	GND	GND	GND
2.30	Open	GND	GND	GND	GND	Open	3.90	Open	GND	GND	GND	GND	GND
2.35	GND	GND	GND	GND	GND	Open	3.95	GND	GND	GND	GND	GND	GND

7.3.2 Adjustable Operation

The TPS7A8300 can be used either with the internal ANY-OUT network or using external resistors. Using the ANY-OUT network allows the TPS7A8300 to be programmed from 0.8 V to 3.95 V. To extend this range of output voltage operation to 5.0 V, external resistors must be used. This configuration is referred to as the adjustable configuration of the TPS7A8300 throughout this document. Regardless whether the internal resistor network or whether external resistors are used, the nominal output voltage of the device is set by two resistors, as shown in Figure 50. Using an internal resistor ensures a 1% matching and minimizes both the number of external components and layout footprint.

Figure 50. Adjustable Operation for Maximum AC Performance

R₁ and R₂ can be calculated for any output voltage range using Equation 2. This resistive network must provide a current equal to or greater than 5 μA for optimum noise performance.

Equation 2. TPS7A8300 q_r1_bvs169.gif

If greater voltage accuracy is required, take into account the output voltage offset contributions resulting from the feedback pin current (I_FB) and use 0.1% tolerance resistors.

Table 3 shows the resistor combination required to achieve a few of the most common rails using commercially-available, 0.1%-tolerance resistors to maximize nominal voltage accuracy while abiding to the formula shown in Equation 2.

Table 3. Recommended Feedback-Resistor Values

V_OUT(TARGET) (V)	FEEDBACK RESISTOR VALUES ⁽¹⁾
V_OUT(TARGET) (V)	R₁ (kΩ)	R₂ (kΩ)
1.00	2.55	10.2
1.20	5.9	11.8
1.50	9.31	10.7
1.80	18.7	15
1.90	15.8	11.5
2.50	24.3	11.5
3.00	31.6	11.5
3.30	35.7	11.5
5.00	105	20

(1) R₁ is connected from OUT to FB; R₂ is connected from FB to GND.

7.3.3 ANY-OUT Operation

Considering the use of the ANY-OUT internal network (where the unit resistance of 1R is equal to 6.05 kΩ) the output voltage is set by grounding the appropriate control pins, as shown in Figure 51. When grounded, all control pins add a specific voltage on top of the internal reference voltage (V_REF = 0.8 V). The output voltage can be equated with Equation 4. Figure 51 and Figure 52 show a 1.2-V and 1-V output voltage, respectively, that provide an example of the circuit usage with and without BIAS voltage. These schematics are described in more detail in the Typical Application section.

TPS7A8300 ai_max_psrr_min_rms_bvs197.gif

Figure 51. ANY-OUT Configuration Circuit
(1.4-V Input, 1.2-V Output, No External BIAS)

Equation 3. V_OUT(NOM) = V_REF + 0.4 V = 0.8 V + 0.4 V = 1.2 V

Figure 52. ANY-OUT Configuration Circuit
(1.1-V Input, 1.0-V Output, 3-V BIAS Voltage)

Equation 4. V_OUT(NOM) = V_REF + 0.2 V = 0.8 V + 0.2 V = 1.0 V

7.3.4 2-A LDO with an Internal Charge Pump

The TPS7A8300 can be used either with the internal resistor network provided, or with the external component as a traditional adjustable LDO. Regardless of the implementation, the TPS7A8300 provides excellent regulation to 1% accuracy, excellent dropout voltage, and high output current capability.

If the input voltage is below 1.4 V, an external BIAS voltage must be supplied to maintain the dropout characteristics. The input voltage or the BIAS voltage is fed through to a internal charge pump to power the internal error amplifier providing the regulation.

7.3.4.1 Dropout Voltage (V_DO)

Generally speaking, the dropout voltage often refers to the voltage difference between the input and output voltage (V_DO = V_IN – V_OUT). However, in the , V_DO is defined as the V_IN – V_OUT voltage at the rated current (I_RATED), where the main current pass-FET is fully on in the ohmic region of operation and is characterized by the classic R_DS(ON) of the FET. V_DO indirectly specifies a minimum input voltage above the nominal programmed output voltage at which the output voltage is expected to remain within its accuracy boundary. If the input falls below this V_DO limit (V_IN < V_OUT + V_DO), then the output voltage decreases in order to follow the input voltage.

Dropout voltage is always determined by the R_DS(ON) of the main pass-FET. Therefore, if the LDO operates below the rated current, then the V_DO for that current scales accordingly. The R_DS(ON) for the TPS7A8300 can be calculated using Equation 5:

Equation 5. TPS7A8300 q_rdson_bvs204.gif

7.3.4.2 Output Voltage Accuracy

Output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected nominal output voltage stated as a percent. This accuracy error includes the errors introduced by the internal reference and the load and line regulation across the full range of rated load and line operating conditions over temperature, unless otherwise specified by the Electrical Characteristics. Output voltage accuracy also accounts for all variations between manufacturing lots.

7.3.4.3 Internal Charge Pump

The internal charge pump ensures proper operation without requiring an external BIAS voltage down to +1.4-V input voltage. Below a 1.4-V input voltage, a BIAS input voltage between 3.0 V and 6.5 V is required. Dropout plots in the ohmic region of the pass-FET are illustrated in the Typical Characteristics section (Figure 12 through Figure 17).

7.3.5 Low-Noise, 0.8-V Reference

The TPS7A8300 includes a low-noise reference ensuring minimal noise during operation because the internal reference is normally the dominant term in noise analysis. Further noise reduction can be achieved using the NR/SS pin and by adding an external C_FF between the SNS pin and the FB pin.

7.3.6 Internal Protection Circuitry

7.3.6.1 Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) circuit monitors the input and bias voltage (V_IN and V_BIAS, respectively) to prevent the device from turning on before V_IN and V_BIAS rise above the lockout voltage. The UVLO circuit also causes a shutdown when V_IN and V_BIAS fall below the lockout voltage.

7.3.6.2 Internal Current Limit (I_(LIM))

The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting in a thermal shutdown of the output.

A foldback feature limits the short-circuit current to protect the regulator from damage under all load conditions. If OUT is forced below 0 V before EN goes high and the load current required exceeds the foldback current limit, the device does not start up. In applications that function with both a positive and negative voltage supply, there are several ways to ensure proper start-up:

Enable the TPS7A8300 first and disable the device last.
Delaying the EN voltage with respect to the IN voltage allows the internal pull-down resistor to discharge any residual voltage at OUT. If a faster discharge rate is required, use an external resistor from OUT to GND.

7.3.6.3 Thermal Protection

The TPS7A8300 contains a thermal shutdown protection circuit to turn off the output current when excessive heat is dissipated in the LDO. Thermal shutdown occurs when the thermal junction temperature (T_J) of the main pass-FET exceeds 160°C (typical). Thermal shutdown hysteresis assures that the LDO resets again (turns on) when the temperature falls to 140°C (typical). The thermal time-constant of the semiconductor die is fairly short, and thus the output cycles on and off at a high rate when thermal shutdown is reached until the power dissipation is reduced.

For reliable operation, limit the junction temperature to a maximum of 125°C. To estimate the thermal margin in a given layout, increase the ambient temperature until the thermal protection shutdown is triggered using worst-case load and highest input voltage conditions. For good reliability, thermal shutdown occurs at least 45°C above the maximum expected ambient temperature condition for the application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TPS7A8300 is designed to protect against thermal overload conditions. The circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A8300 into thermal shutdown degrades device reliability.

7.3.7 Programmable Soft-Start

Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO exceed the respective threshold voltage. The noise-reduction capacitor (C_NR/SS) serves a dual purpose of both governing output noise reduction and programming the soft-start ramp during turn-on. See the Application and Implementation section on implementing a soft-start.

7.3.8 Power-Good Function

The TPS7A8300 has a power-good function that works by toggling the state of the PG output pin. When the output voltage falls below the PG threshold voltage (V_IT(PG)), the PG pin open-drain output engages (low impedance to GND). When the output voltage exceeds the V_IT(PG) threshold by an amount greater than V_HYS(PG), the PG pin becomes high-impedance. By connecting a pull-up resistor to an external supply, any downstream device can receive PG as a logic signal. Make sure that the external pull-up supply voltage results in a valid logic signal for the receiving device or devices. Use a pull-up resistor from 10 kΩ to 100 kΩ for best results.

When employing the feed-forward capacitor (C_FF), the turn-on time-constant for the LDO is increased and the power-good output time-constant stays the same, resulting in an invalid status of the LDO. To avoid this issue and receive a valid PG output, ensure that the time-constant of both the LDO and the power-good output match. For more details, see application report, Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator, SBVA042.

7.3.9 Integrated Resistance Network (ANY-OUT)

An internal resistance network is provided allowing the TPS7A8300 output voltage to be programmed easily between 0.8 V to 3.95 V with a 50-mV step.

7.4 Device Functional Modes

7.4.1 Operation with 1.1 V > V_IN > 1.4 V

The TPS7A8300 requires a bias voltage on the BIAS pin ≥ 3.0 V if the high-current input supply voltage is between 1.1 to 1.4 V. The bias voltage pin consumes 2.3 mA, nominally.

7.4.2 Operation with 1.4 V ≥ V_IN > 6.5 V

If the input voltage is equal to, or exceeds 1.4 V, no bias voltage is necessary. The device is automatically selected to be powered from the IN pin in this condition and the BIAS pin can be left floating.

7.4.3 Disabled

If the voltage on the EN pin is less than 0.5 V, the device is disabled and the output is high impedance. The output impedance of the LDO is then set by the gain setting resistors if a path to GND is provided between OUT and GND. Raising EN above 1.1 V (maximum) initiates the startup sequence of the device. In this state, quiescent current does not exceed 2.5 µA.