TPS7A8300 2-A, 6-µVRMS, RF, LDO Voltage Regulator

7.3.1 ANY-OUT Programmable Output Voltage

The TPS7A8300 does not require external resistors to set output voltage, which is typical of adjustable low-dropout voltage regulators (LDOs). However, the TPS7A8300 uses pins 5, 6, 7, 9, 10, and 11 to program the regulated output voltage. Each pin is either connected to ground (active) or left open (floating). ANY-OUT programming is set by Equation 1 as the sum of the internal reference voltage (V_REF = 0.8 V) plus the accumulated sum of the respective voltages assigned to each active pin; that is, 50mV (pin 5), 100mV (pin 6), 200mV (pin 7), 400mV (pin 9), 800mV (pin 10), or 1.6V (pin 11). Table 1 summarizes these voltage values associated with each active pin setting for reference. By leaving all program pins open, or floating, the output is thereby programmed to the minimum possible output voltage equal to V_REF.

Equation 1.

Table 2 provides a full list of target output voltages and corresponding pin settings. The voltage setting pins have a binary weight; therefore, the output voltage can be programmed to any value from 0.8 V to 3.95 V in 50-mV steps.

There are several alternative ways to set the output voltage. The program pins can be driven using external general-purpose input/output pins (GPIOs), manually connected to ground using 0-Ω resistors (or left open), or hardwired by the given layout of the printed circuit board (PCB) to set the ANY-OUT voltage.

7.3.2 Adjustable Operation

The TPS7A8300 can be used either with the internal ANY-OUT network or using external resistors. Using the ANY-OUT network allows the TPS7A8300 to be programmed from 0.8 V to 3.95 V. To extend this range of output voltage operation to 5.0 V, external resistors must be used. This configuration is referred to as the adjustable configuration of the TPS7A8300 throughout this document. Regardless whether the internal resistor network or whether external resistors are used, the nominal output voltage of the device is set by two resistors, as shown in Figure 50. Using an internal resistor ensures a 1% matching and minimizes both the number of external components and layout footprint.

Figure 50. Adjustable Operation for Maximum AC Performance

R₁ and R₂ can be calculated for any output voltage range using Equation 2. This resistive network must provide a current equal to or greater than 5 μA for optimum noise performance.

Equation 2.

If greater voltage accuracy is required, take into account the output voltage offset contributions resulting from the feedback pin current (I_FB) and use 0.1% tolerance resistors.

Table 3 shows the resistor combination required to achieve a few of the most common rails using commercially-available, 0.1%-tolerance resistors to maximize nominal voltage accuracy while abiding to the formula shown in Equation 2.

7.3.3 ANY-OUT Operation

Considering the use of the ANY-OUT internal network (where the unit resistance of 1R is equal to 6.05 kΩ) the output voltage is set by grounding the appropriate control pins, as shown in Figure 51. When grounded, all control pins add a specific voltage on top of the internal reference voltage (V_REF = 0.8 V). The output voltage can be equated with Equation 4. Figure 51 and Figure 52 show a 1.2-V and 1-V output voltage, respectively, that provide an example of the circuit usage with and without BIAS voltage. These schematics are described in more detail in the Typical Application section.

Figure 51. ANY-OUT Configuration Circuit
(1.4-V Input, 1.2-V Output, No External BIAS)

Figure 52. ANY-OUT Configuration Circuit
(1.1-V Input, 1.0-V Output, 3-V BIAS Voltage)

7.3.4 2-A LDO with an Internal Charge Pump

The TPS7A8300 can be used either with the internal resistor network provided, or with the external component as a traditional adjustable LDO. Regardless of the implementation, the TPS7A8300 provides excellent regulation to 1% accuracy, excellent dropout voltage, and high output current capability.

If the input voltage is below 1.4 V, an external BIAS voltage must be supplied to maintain the dropout characteristics. The input voltage or the BIAS voltage is fed through to a internal charge pump to power the internal error amplifier providing the regulation.

7.3.4.1 Dropout Voltage (V_DO)

Generally speaking, the dropout voltage often refers to the voltage difference between the input and output voltage (V_DO = V_IN – V_OUT). However, in the , V_DO is defined as the V_IN – V_OUT voltage at the rated current (I_RATED), where the main current pass-FET is fully on in the ohmic region of operation and is characterized by the classic R_DS(ON) of the FET. V_DO indirectly specifies a minimum input voltage above the nominal programmed output voltage at which the output voltage is expected to remain within its accuracy boundary. If the input falls below this V_DO limit (V_IN < V_OUT + V_DO), then the output voltage decreases in order to follow the input voltage.

Dropout voltage is always determined by the R_DS(ON) of the main pass-FET. Therefore, if the LDO operates below the rated current, then the V_DO for that current scales accordingly. The R_DS(ON) for the TPS7A8300 can be calculated using Equation 5:

Equation 5.

7.3.5 Low-Noise, 0.8-V Reference

The TPS7A8300 includes a low-noise reference ensuring minimal noise during operation because the internal reference is normally the dominant term in noise analysis. Further noise reduction can be achieved using the NR/SS pin and by adding an external C_FF between the SNS pin and the FB pin.

7.3.6 Internal Protection Circuitry

7.3.7 Programmable Soft-Start

Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO exceed the respective threshold voltage. The noise-reduction capacitor (C_NR/SS) serves a dual purpose of both governing output noise reduction and programming the soft-start ramp during turn-on. See the Application and Implementation section on implementing a soft-start.

7.3.8 Power-Good Function

The TPS7A8300 has a power-good function that works by toggling the state of the PG output pin. When the output voltage falls below the PG threshold voltage (V_IT(PG)), the PG pin open-drain output engages (low impedance to GND). When the output voltage exceeds the V_IT(PG) threshold by an amount greater than V_HYS(PG), the PG pin becomes high-impedance. By connecting a pull-up resistor to an external supply, any downstream device can receive PG as a logic signal. Make sure that the external pull-up supply voltage results in a valid logic signal for the receiving device or devices. Use a pull-up resistor from 10 kΩ to 100 kΩ for best results.

When employing the feed-forward capacitor (C_FF), the turn-on time-constant for the LDO is increased and the power-good output time-constant stays the same, resulting in an invalid status of the LDO. To avoid this issue and receive a valid PG output, ensure that the time-constant of both the LDO and the power-good output match. For more details, see application report, Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator, SBVA042.

7.3.9 Integrated Resistance Network (ANY-OUT)

An internal resistance network is provided allowing the TPS7A8300 output voltage to be programmed easily between 0.8 V to 3.95 V with a 50-mV step.

7.4.1 Operation with 1.1 V > V_IN > 1.4 V

The TPS7A8300 requires a bias voltage on the BIAS pin ≥ 3.0 V if the high-current input supply voltage is between 1.1 to 1.4 V. The bias voltage pin consumes 2.3 mA, nominally.

7.4.2 Operation with 1.4 V ≥ V_IN > 6.5 V

If the input voltage is equal to, or exceeds 1.4 V, no bias voltage is necessary. The device is automatically selected to be powered from the IN pin in this condition and the BIAS pin can be left floating.

7.4.3 Disabled

If the voltage on the EN pin is less than 0.5 V, the device is disabled and the output is high impedance. The output impedance of the LDO is then set by the gain setting resistors if a path to GND is provided between OUT and GND. Raising EN above 1.1 V (maximum) initiates the startup sequence of the device. In this state, quiescent current does not exceed 2.5 µA.

8.1.1 Start-Up

8.1.1.3 Soft-Start and Inrush Current

Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO achieve threshold voltage. The noise-reduction capacitor serves a dual purpose of both governing output noise reduction and programming the soft-start ramp during turn-on.

Inrush current is defined as the current into the LDO at the IN pin during start-up. Inrush current then consists primarily of the sum of load and current used to charge the output capacitor. This current is difficult to measure because the input capacitor must be removed, which is not recommended. However, this soft-start current can be estimated by Equation 7:

Equation 7.

where

• V_OUT(t) is the instantaneous output voltage of the turn-on ramp,
• dV_OUT(t) / dt is the slope of the V_OUT ramp, and
• R_LOAD is the resistive load impedance.

8.1.2 Capacitor Recommendation

The TPS7A8300 is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input, output, and noise-reduction pin (NR, pin 13). Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged precisely because the capacitance varies so widely. In all cases, ceramic capacitance varies a great deal with operating voltage and temperature and the design engineer must be aware of these characteristics. As a rule of thumb, ceramic capacitors are recommended to be derated by 50%. To compensate for this derating, increase capacitor value by 100%. The input and output capacitors recommended herein account for a capacitance derating of 50%.

Attention must be given to the input capacitance to minimize transient input droop during load current steps. Input capacitances of 10 µF or greater provide the desired effect and do not affect stability. Note that simply using large ceramic input capacitances can also cause unwanted ringing at the output if the input capacitor (in combination with the wire-lead inductance) creates a high-Q peaking effect during transients. For example, a 5-nH lead inductance and a 10-µF input capacitor form an LC filter with a resonance frequency of 712 kHz that is near the edge of the open-loop bandwidth. Short, well-designed interconnect traces to the up-stream supply minimize this effect without adding damping. Damping of unwanted ringing can be accomplished by using a tantalum capacitor, with a few hundred milliohms of ESR, in parallel with the ceramic input capacitor.

8.1.3 AC Performance

The LDO ac performance is typically understood to include power-supply rejection ratio, load step transient response, and output noise. These metrics are primarily a function of open-loop gain and bandwidth, phase margin, and reference noise.

8.1.3.1 Power-Supply Ripple Rejection (PSRR)

PSRR is a measure of how well the LDO control loop rejects ripple noise from the input source to make the dc output voltage as noise-free as possible across the frequency spectrum (usually 10 Hz to 10 MHz). Even though PSRR is therefore a loss in noise signal amplitude (the output ripple relative to the input ripple), the PSRR reciprocal is plotted in the Electrical Characteristics as a positive number in decibels (dB) for convenience. Equation 8 gives the PSRR calculation as a function of frequency where input noise voltage [V_S(IN)(f)] and output noise voltage [V_S(OUT)(f)] are understood to be purely ac signals.

Equation 8.

Noise that couples from the input to the internal reference voltage for the control loop is also a primary contributor to reduced PSRR magnitude and bandwidth. This reference noise is greatly filtered by the noise-reduction capacitor at the NR pin of the LDO in combination with an internal filter resistor (R_SS) for improved PSRR.

The LDO is often employed not only as a dc-dc regulator, but also to provide exceptionally clean power-supply voltages that exhibit ultra-low noise and ripple to power-sensitive system components. This usage is especially true for the TPS7A8300.

8.1.4 Power Dissipation (P_D)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses.

To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. P_D can be calculated using Equation 9:

Equation 9.

An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system voltage rails. Proper selection allows the minimum input voltage necessary for output regulation to be obtained.

The primary heat conduction path for the VQFN (RGW and RGR) package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any inner plane areas or to a bottom-side copper plane.

The maximum power dissipation determines the maximum allowable junction temperature (T_J) for the device. Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (θ_JA) of the combined PCB and device package and the temperature of the ambient air (T_A), according to Equation 10.

Equation 10.

Unfortunately, this thermal resistance (θ_JA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The θ_JA recorded in the Thermal Information table is determined by the JEDEC standard, PCB, and copper-spreading area and is only used as a relative measure of package thermal performance. Note that for a well-designed thermal layout, θ_JA is actually the sum of the VQFN package junction-to-case (bottom) thermal resistance (θ_JCbot) plus the thermal resistance contribution by the PCB copper. When θ_JCbot is known, the amount of heat-sinking area required can be estimated for a given θ_JA, as shown in Figure 53. θ_JCbot can be found in the Thermal Information table.

NOTE: The θ_JA value at a board size of 9-in² (that is, 3-in × 3-in) is a JEDEC standard.

Figure 53. θ_JA versus Board Size

8.1.5 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JT and Ψ_JB) are given in the Thermal Information table and are used in accordance with Equation 11.

Equation 11.

where

• P_D is the power dissipated as explained in Equation 9,
• T_T is the temperature at the center-top of the device package, and
• T_B is the PCB surface temperature measured 1 mm from the device package and centered on the package edge.

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 4 as the input parameters.

8.2.2 Detailed Design Procedure

At 1.6 A, the dropout of the TPS7A8300 has 150 mV maximum dropout over temperature, thus a 200-mV headroom is sufficient for operation over both input and output voltage accuracy. The efficiency of the TPS7A8300 in this configuration is V_OUT / V_IN = 85.7%.

To achieve the smallest form factor, the 3.5-mm × 3.5-mm² RGR package is selected. The ANY-OUT internal resistor network is also used.

To achieve 1.2 V on the output, the 400mV pin is grounded. The voltage value of 400 mV is added to the 0.8-V internal reference voltage for V_OUT(NOM) equal to 1.2 V; as described in Equation 12.

Input and output capacitors are selected in accordance with the Capacitor Recommendation section. Ceramic capacitances of 10 µF for the input and three 10-µF capacitors for the output are selected.

To satisfy the required startup time and still maintain low noise performance, a 10-nF C_NR/SS is selected. This value is calculated with Equation 13.

With an efficiency of 85.7% and a 1.6-A maximum load, the internal power dissipation is 320 mW, which corresponds to a 11.3°C junction temperature rise for the RGR package. With an 85°C maximum ambient temperature, the junction temperature is at 96.3°C. To minimize noise, a feed-forward capacitance (C_FF) of 10 nF is selected.

8.2.3 Application Curves

Figure 55. Output Load Transient Response

Figure 56. 10-Hz to 100-kHz Output Noise Voltage, 1.6-A Load Current