The TMUX7234 is a complementary metal-oxide semiconductor (CMOS) multiplexer with latch-up immunity. The TMUX7234 contains four independently controlled SPDT switches with an EN pin to enable or disable all four channels. The device supports single supply (4.5 V to 44 V), dual supplies (±4.5 V to ±22 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The TMUX7234 supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from VSS to VDD.
All logic control inputs support logic levels from 1.8 V to VDD, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage.
The TMUX72xx family provides latch-up immunity, preventing undesirable high current events between parasitic structures within the device typically caused by overvoltage events. A latch-up condition typically continues until the power supply rails are turned off and can lead to device failure. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments.
PART NUMBER | PACKAGE(1) | PACKAGE SIZE(2) |
---|---|---|
TMUX7234 | PW (TSSOP, 20) | 6.5 mm × 6.4 mm |
RRQ (WQFN, 20) | 4 mm × 4 mm |
PIN | TYPE(1) | DESCRIPTION(2) | ||
---|---|---|---|---|
NAME | PW NO. | RRQ NO. | ||
SEL1 | 1 | 19 | I | Logic control input 1; has internal pull-down resistor. Controls switch 1 (see Section 7.5). |
S1A | 2 | 20 | I/O | Source pin 1A. Can be an input or output. |
D1 | 3 | 1 | I/O | Drain pin 1. Can be an input or output. |
S1B | 4 | 2 | I/O | Source pin 1B. Can be an input or output. |
VSS | 5 | 3 | P | Negative power supply. This pin has the most negative power-supply potential. This pin can be connected to ground in single supply applications. Connect a decoupling capacitor ranging from 0.1 μF to 10 μF between VSS and GND for reliable operation. |
GND | 6 | 4 | P | Ground (0 V) reference. |
S2B | 7 | 5 | I/O | Source pin 2B. Can be an input or output. |
D2 | 8 | 6 | I/O | Drain pin 2. Can be an input or output. |
S2A | 9 | 7 | I/O | Source pin 2A. Can be an input or output. |
SEL2 | 10 | 8 | I | Logic control input 2; has internal pull-down resistor. Controls switch 2 (see Section 7.5). |
SEL3 | 11 | 9 | I | Logic control input 3; has internal pull-down resistor. Controls switch 3 (see Section 7.5). |
S3A | 12 | 10 | I/O | Source pin 3A. Can be an input or output. |
D3 | 13 | 11 | I/O | Drain pin 3. Can be an input or output. |
S3B | 14 | 12 | I/O | Source pin 3B. Can be an input or output. |
EN | 15 | 18 | I | Active low logic enable; has internal pull-down resistor. The SELx logic inputs determine switch connections when this pin is low (see Section 7.5). |
VDD | 16 | 13 | P | Positive power supply. This pin has the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 μF to 10 μF between VDD and GND. |
S4B | 17 | 14 | I/O | Source pin 4B. Can be an input or output. |
D4 | 18 | 15 | I/O | Drain pin 4. Can be input or output |
S4A | 19 | 16 | I/O | Source pin 4A. Can be an input or output. |
SEL4 | 20 | 17 | I | Logic control input 4, has internal pull-down resistor. Controls switch 4 (see Section 7.5). |
Thermal Pad | — | The thermal pad is not connected internally. There is no requirement to solder this pad. If connected, it is recommended to leave the pad floating or tied to GND. |