Systems can have multiple digital voltages that are similar in value which need to be separated for optimal performance. For example, an incoming 3.3-V signal may need to communicate with an internally regulated 3.3-V device, and the two may vary separately from 3 V to 3.6 V. In this case, true isolation is not required, however separation of the voltage nodes will prevent issues from the voltage mismatch.
Part Number | AEC-Q100 | VCC Range | Channels | Features |
---|---|---|---|---|
SN74LVC1G34 | 1.65 V – 5.5 V | 1 | Over-voltage tolerant inputs Partial power down (Ioff) Balanced high-drive CMOS outputs (up to 32 mA) |
|
SN74LVC1G17-Q1 | ✓ | 1.65 V – 5.5 V | 1 |
Schmitt-trigger input Over-voltage tolerant input Partial power down (Ioff) |
SN74LVC1G07 | 1.65 V – 5.5 V | 1 |
Open-drain output Over-voltage tolerant input and output Partial power down (Ioff) |
|
SN74LVC1G07-Q1 | ✓ | |||
SN74LV244A | 2 V – 5.5 V | 8 |
Over-voltage tolerant inputs Partial power down (Ioff) Balanced high-drive CMOS outputs (up to 16 mA) |
|
SN74LV244A-Q1 | ✓ | |||
SN74LVC16244A | 1.65 V – 3.6 V | 16 |
Over-voltage tolerant inputs Partial power down (Ioff) Balanced high-drive CMOS outputs (up to 24 mA) |
|
SN74LVC16244A-Q1 | ✓ |
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