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I2C is a standard method of communication between multiple ICs within a system. It leverages a bus architecture with a controller device and either a single target or multiple target devices (see Figure 1-1). In some circumstances, the controller device and the target device may use two different voltage levels for I2C communication. In that case, the TCA9517 may be used to properly translate the voltage levels (see Figure 1-2). The TCA9517 is a buffered level-translator, meaning the device not only shifts the voltage levels to the needs of each device, but it also re-drives the signals in both directions. This buffer aspect of the TCA9517 can introduce propagation delays into the communication, which can result in visible SDA handoffs when recorded on an oscilloscope. This article explains what to expect on the SDA lines when the TCA9517 is used and if the result of the propagation delays from buffers like the TCA9517 are something to be concerned about.
During an I2C transaction, after the controller sends out the I2C address to the target device, the target should respond with an Acknowledge (ACK) to let the controller know the target recognizes its address and to signal to the controller to continue the transaction. This document focuses specifically on the ACK response from the target. Figure 2-1 shows the beginning of I2C communication between an I2C controller and I2C target in which the controller sends the address and the target responds with an ACK.
On the falling edge of the eighth clock cycle, the target takes control of the bus to signal to the controller that it has Acknowledged its address was called. Figure 2-2 shows the target driving the SDA line low after a short delay on the falling edge of the eighth clock pulse.
The yellow box shows illustrates the controller driving the SCL and SDA line low during a write transaction. The red box shows that there is a short period of time where both the controller and target have control of the bus after the eighth clock pulse, essentially an overlap of SDA being driven low by both controller and target. The purple box shows that the target has total control of the bus well before the start of the ninth clock pulse and through the duration of the ninth clock pulse. In this example, the open drain drivers of both the controller and the target overlapped and drove the SDA line low during the red box. This kind of example is common and occurs when the controller releases the SDA line after the target device drives the SDA line low.
When the TCA9517 is added to the system for level translation or for redriving purposes, it introduces a propagation delay due to the integrated buffer design. Figure 3-1 shows an exaggerated timing diagram for the SCL and SDA lines with propagation delay added to the timing.
From a data integrity standpoint, the signal delay does not impact the ability for the controller and target to communicate properly because the delay is equal for both the SCL and SDA lines. From a timing perspective, the SDA line remains stable for the entire portion of the SCL high period for the target device.
The propagation delay does impact the timing for the target device to take control of the bus during the ACK portion of the signaling with respect to the controller. Figure 3-2 shows a zoomed-in illustration of what occurs after the falling edge of the eighth clock pulse. After the falling edge of the eighth clock pulse, the open-drain driver of the controller needs to tri-state to give up control of the SDA line so that the target can take control of the SDA signal to ACK to the controller. However, there is a delay before the target receives the message to take control of the bus.
This delay in the SCL line being received by the target may result in a small window where the controller has released control of SDA, but the target has not yet taken control of the SDA signal yet because it has not seen the SCL signal go low. Figure 3-3 shows how this circumstance occurs in the system.
During the window where the controller has released control of the bus and the target has not taken control of the bus, the SDA line on the side of the controller begins to rise. This occurs on the A side of the TCA9517, since there are no other external open-drain drivers driving the SDA line low. Before the rising SDA signal is able to traverse through the TCA9517 from the A side to the B side, the SCL signal has already reached the target device to signal for the target to take control of the bus. At this point, the target is able to take control of SDA before the SDA line starts to rise on the target side (the B side of the TCA9517 in this example).