TCA9539 Low Voltage 16-Bit I2C and SMBus Low-Power I/O Expander with Interrupt Output, Reset Pin, and Configuration Registers
- SCPS202C October 2009 – May 2016 TCA9539
  
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DATA SHEET

TCA9539 Low Voltage 16-Bit I2C and SMBus Low-Power I/O Expander with Interrupt Output, Reset Pin, and Configuration Registers

1 Features

I²C to Parallel Port Expander
Low Standby-Current Consumption
Open-Drain Active-Low Interrupt Output
Active-Low Reset Input
5-V Tolerant I/O Ports
Compatible With Most Microcontrollers
400-kHz Fast I²C Bus
Input and Output Configuration Register
Polarity Inversion Register
Internal Power-on Reset
No Glitch on Power Up
Noise Filter on SCL and SDA Inputs
Address by Two Hardware Address Pins for Use of up to Four Devices
Latched Outputs With High-Current Drive Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

2 Applications

Servers
Routers (Telecom Switching Equipment)
Personal Computers, smartphones
Industrial Automation
I²C GPIO Expansion

3 Description

The TCA9539 is a 24-pin device that provides 16 bits of general purpose parallel input and output (I/O) expansion for the two-line bidirectional I²C bus (or SMBus protocol). The device can operate with a power supply voltage (V_CC) range from 1.65 V to 5.5 V. The device supports 100-kHz (I²C Standard mode) and 400-kHz (I²C Fast mode) clock frequencies. I/O expanders such as the TCA9539 provide a simple solution when additional I/Os are needed for switches, sensors, push-buttons, LEDs, fans, and other similar devices.

The features of the TCA9539 include an interrupt that is generated on the INT pin whenever an input port changes state. The A0 and A1 hardware selectable address pins allow up to four TCA9539 devices on the same I²C bus. The device can be reset to its default state by cycling the power supply and causing a power-on-reset. Also, the TCA9539 has a hardware RESET pin that can be used to reset the device to its default state.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TCA9539	TSSOP (24)	7.80 mm × 4.40 mm
	WQFN (24)	4.00 mm × 4.00 mm
	VQFN (24)	4.00 mm × 4.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

TCA9539 Application_schematic_SCPS202C.gif

4 Revision History

Changes from B Revision (October 2015) to C Revision

Made changes to Interrupt (INT) Output and Reads sectionGo
Made changes to Recommended Operating ConditionsGo
Made changes to Electrical CharacteristicsGo
Added I_OL for different T_j Go
Removed ΔI_CC spec from the Electrical Characteristics table, added ΔI_CC typical characteristics graph Go
Changed I_CC standby into different input states, with increased maximums Go
Changed C_io maximum Go
Clarified interrupt reset time (t_ir) with respect to falling edge of ACK related SCL pulse. Go
Updated Figure 33 and Figure 34Go
Power on reset requirements relaxed Go

Changes from A Revision (September 2009) to B Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go
Added RGE package.Go
Added Thermal Information table Go
Added "Time to reset; V_CC = 1.65 V - 2.3 V" parameter to RESET Timing Requirements table. Go
Added "Output data valid; V_CC = 1.65 V - 2.3 V to Switching Characteristics table. Go

5 Pin Configuration and Functions

PW Package

24-Pins TSSOP

Top View

RTW, RGE Package

24-Pins WQFN, VQFN

Top View

Pin Functions

NAME	NO.		I/O	DESCRIPTION
NAME	TSSOP (PW)	QFN (RTW, RGE)	I/O	DESCRIPTION
A0	21	18	I	Address input. Connect directly to V_CC or ground
A1	2	23	I	Address input. Connect directly to V_CC or ground
GND	12	9	—	Ground
INT	1	22	O	Interrupt open-drain output. Connect to V_CC through a pull-up resistor
RESET	3	24	I	Active-low reset input. Connect to V_CC through a pull-up resistor if no active connection is used
P00	4	1	I/O	P-port input-output. Push-pull design structure. At power on, P00 is configured as an input
P01	5	2	I/O	P-port input-output. Push-pull design structure. At power on, P01 is configured as an input
P02	6	3	I/O	P-port input-output. Push-pull design structure. At power on, P02 is configured as an input
P03	7	4	I/O	P-port input-output. Push-pull design structure. At power on, P03 is configured as an input
P04	8	5	I/O	P-port input-output. Push-pull design structure. At power on, P04 is configured as an input
P05	9	6	I/O	P-port input-output. Push-pull design structure. At power on, P05 is configured as an input
P06	10	7	I/O	P-port input-output. Push-pull design structure. At power on, P06 is configured as an input
P07	11	8	I/O	P-port input-output. Push-pull design structure. At power on, P07 is configured as an input
P10	13	10	I/O	P-port input-output. Push-pull design structure. At power on, P10 is configured as an input
P11	14	11	I/O	P-port input-output. Push-pull design structure. At power on, P11 is configured as an input
P12	15	12	I/O	P-port input-output. Push-pull design structure. At power on, P12 is configured as an input
P13	16	13	I/O	P-port input-output. Push-pull design structure. At power on, P13 is configured as an input
P14	17	14	I/O	P-port input-output. Push-pull design structure. At power on, P14 is configured as an input
P15	18	15	I/O	P-port input-output. Push-pull design structure. At power on, P15 is configured as an input
P16	19	16	I/O	P-port input-output. Push-pull design structure. At power on, P16 is configured as an input
P17	20	17	I/O	P-port input-output. Push-pull design structure. At power on, P17 is configured as an input
SCL	22	19	I	Serial clock bus. Connect to V_CC through a pull-up resistor
SDA	23	20	I/O	Serial data bus. Connect to V_CC through a pull-up resistor
V_CC	24	21	—	Supply voltage

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

			MIN	MAX	UNIT
V_CC	Supply voltage		–0.5	6	V
V_I	Input voltage⁽²⁾		–0.5	6	V
V_O	Output voltage ⁽²⁾		–0.5	6	V
I_IK	Input clamp current	V_I < 0		–20	mA
I_OK	Output clamp current	V_O < 0		–20	mA
I_IOK	Input-output clamp current	V_O < 0 or V_O > V_CC		±20	mA
I_OL	Continuous output low current	V_O = 0 to V_CC		50	mA
I_OH	Continuous output high current	V_O = 0 to V_CC		–50	mA
I_CC	Continuous current through GND			–250	mA
I_CC	Continuous current through V_CC			160	mA
T_j(MAX)	Maximum junction temperature			100	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101 ⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

				MIN	MAX	UNIT
V_CC	Supply voltage			1.65	5.5	V
V_IH	High-level input voltage	SCL, SDA		0.7 × V_CC	V_CC ^⁽¹⁾	V
V_IH	High-level input voltage	A0, A1, RESET, P07–P00, P10–P17		0.7 × V_CC	5.5	V
V_IL	Low-level input voltage	SCL, SDA, A0, A1, RESET, P07–P00, P10–P17		–0.5	0.3 × V_CC	V
I_OH	High-level output current	P07–P00, P17–P10			–10	mA
I_OL	Low-level output current⁽²⁾	P00–P07, P10–P17	T_j ≤ 65°C		25	mA
			T_j ≤ 85°C		18
			T_j ≤ 100°C		11
I_OL	Low-level output current⁽²⁾	INT, SDA	T_j ≤ 85°C		6	mA
I_OL	Low-level output current⁽²⁾	INT, SDA	T_j ≤ 100°C		3.5	mA
T_A	Operating free-air temperature			–40	85	°C

(1) For voltages applied above V_CC, an increase in I_CC will result.

(2) The values shown apply to specific junction temperatures, which depend on the R_θJA of the package used. See the Calculating Junction Temperature and Power Dissipation section on how to calculate the junction temperature.

6.4 Thermal Information

THERMAL METRIC ⁽¹⁾		TCA9539			UNIT
		PW (TSSOP)	RTW (WQFN)	RGE (VQFN)
		24 PINS	24 PINS	24 PINS
R_θJA	Junction-to-ambient thermal resistance	108.8	43.6	48.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	54.	46.2	58.1	°C/W
R_θJB	Junction-to-board thermal resistance	62.8	22.1	27.1	°C/W
ψ_JT	Junction-to-top characterization parameter	11.1	1.5	3.3	°C/W
ψ_JB	Junction-to-board characterization parameter	62.3	22.2	27.2	°C/W
R_θJC(bottom)	Junction-to-case (bottom) thermal resistance	—	10.7	15.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		V_CC	MIN	TYP ⁽¹⁾	MAX	UNIT
V_IK	Input diode clamp voltage	I_I = –18 mA		1.65 V to 5.5 V	–1.2			V
V_PORR	Power-on reset voltage, V_CC rising	V_I = V_CC or GND, I_O = 0		1.65 V to 5.5 V		1.2	1.5	V
V_PORF	Power-on reset voltage, V_CC falling	V_I = V_CC or GND, I_O = 0		1.65 V to 5.5 V	0.75	1		V
V_OH	P-port high-level output voltage ⁽²⁾	I_OH = –8 mA		1.65 V	1.2			V
				2.3 V	1.8
				3 V	2.6
				4.75 V	4.1
		I_OH = –10 mA		1.65 V	1
				2.3 V	1.7
				3 V	2.5
				4.75 V	4
I_OL	SDA	V_OL = 0.4 V		1.65 V to 5.5 V	3			mA
	P port ⁽³⁾	V_OL = 0.5 V		1.65 V to 5.5 V	8
	P port ⁽³⁾	V_OL = 0.7 V		1.65 V to 5.5 V	10
	INT	V_OL = 0.4 V			3
I_I	SCL, SDA	V_I = V_CC or GND		1.65 V to 5.5 V			±1	μA
I_I	A0, A1, RESET	V_I = V_CC or GND		1.65 V to 5.5 V			±1	μA
I_IH	P port	V_I = V_CC		1.65 V to 5.5 V			1	μA
I_IL	P port	V_I = GND		1.65 V to 5.5 V			–1	μA
I_CC	Operating mode	V_I = V_CC or GND, I_O = 0, I/O = inputs, f_SCL = 400 kHz, no load		5.5 V		22	40	μA
				3.6 V		11	30
				2.7 V		8	19
				1.95 V		5	11
	Standby mode	V_I = V_CC or GND, I_O = 0, I/O = inputs, f_SCL = 0 kHz, no load	V_I = V_CC	5.5 V		1.5	3.9
				3.6 V		0.9	2.2
				2.7 V		0.6	1.8
				1.95 V		0.4	1.5
			V_I = GND	5.5 V		1.5	8.7
				3.6 V		0.9	4
				2.7 V		0.6	3
				1.95 V		0.4	2.2
C_i	SCL	V_I = V_CC or GND		1.65 V to 5.5 V		3	8	pF
C_io	SDA	V_IO = V_CC or GND		1.65 V to 5.5 V		3	9.5	pF
C_io	P port	V_IO = V_CC or GND		1.65 V to 5.5 V		3.7	9.5	pF

(1) All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V V_CC) and T_A = 25°C.

(2) Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximum current of 100 mA, for a device total of 200 mA.

(3) The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).

6.6 I²C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 19)

			MIN	MAX	UNIT
I²C BUS—STANDARD MODE
f_scl	I²C clock frequency		0	100	kHz
t_sch	I²C clock high time		4		µs
t_scl	I²C clock low time		4.7		µs
t_sp	I²C spike time			50	ns
t_sds	I²C serial-data setup time		250		ns
t_sdh	I²C serial-data hold time		0		ns
t_icr	I²C input rise time			1000	ns
t_icf	I²C input fall time			300	ns
t_ocf	I²C output fall time	10-pF to 400-pF bus		300	ns
t_buf	I²C bus free time between stop and start		4.7		µs
t_sts	I²C start or repeated start condition setup		4.7		µs
t_sth	I²C start or repeated start condition hold		4		µs
t_sps	I²C stop condition setup		4		µs
t_vd(data)	Valid data time	SCL low to SDA output valid		3.45	µs
t_vd(ack)	Valid data time of ACK condition	ACK signal from SCL low to SDA (out) low		3.45	µs
C_b	I²C bus capacitive load			400	pF

			MIN	MAX	UNIT
I²C BUS—FAST MODE
f_scl	I²C clock frequency		0	400	kHz
t_sch	I²C clock high time		0.6		µs
t_scl	I²C clock low time		1.3		µs
t_sp	I²C spike time			50	ns
t_sds	I²C serial-data setup time		100		ns
t_sdh	I²C serial-data hold time		0		ns
t_icr	I²C input rise time		20	300	ns
t_icf	I²C input fall time		20 × (V_CC / 5.5 V)	300	ns
t_ocf	I²C output fall time	10-pF to 400-pF bus	20 × (V_CC / 5.5 V)	300	ns
t_buf	I²C bus free time between stop and start		1.3		µs
t_sts	I²C start or repeated start condition setup		0.6		µs
t_sth	I²C start or repeated start condition hold		0.6		µs
t_sps	I²C stop condition setup		0.6		µs
t_vd(data)	Valid data time	SCL low to SDA output valid		0.9	µs
t_vd(ack)	Valid data time of ACK condition	ACK signal from SCL low to SDA (out) low		0.9	µs
C_b	I²C bus capacitive load			400	pF

6.7 RESET Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 22)

		MIN	UNIT
t_W	Reset pulse duration	6	ns
t_REC	Reset recovery time	0	ns
t_RESET	Time to reset; for V_CC = 2.3 V - 5.5 V	400	ns
t_RESET	Time to reset; for V_CC = 1.65 V - 2.3 V	550	ns

6.8 Switching Characteristics

over recommended operating free-air temperature range, C_L ≤ 100 pF (unless otherwise noted) (see Figure 20 and Figure 21)

PARAMETER		FROM (INPUT)	TO (OUTPUT)	MIN	MAX	UNIT
t_iv	Interrupt valid time	P port	INT		4	μs
t_ir	Interrupt reset delay time	SCL	INT		4	μs
t_pv	Output data valid; For V_CC = 2.3 V - 5.5 V	SCL	P port		200	ns
t_pv	Output data valid; For V_CC = 1.65 V - 2.3 V	SCL	P port		300	ns
t_ps	Input data setup time	P port	SCL	150		ns
t_ph	Input data hold time	P port	SCL	1		μs

6.9 Typical Characteristics

T_A = 25°C (unless otherwise noted)

Figure 1. Supply Current vs Temperature for Different Supply Voltage (V_CC)

Figure 3. Supply Current vs Supply Voltage for Different Temperature (T_A)

Figure 5. I/O Sink Current vs Output Low Voltage for Different Temperature (T_A) for V_CC = 1.8 V

Figure 7. I/O Sink Current vs Output Low Voltage for Different Temperature (T_A) for V_CC = 3.3 V

Figure 9. I/O Sink Current vs Output Low Voltage for Different Temperature (T_A) for V_CC = 5.5 V

Figure 11. I/O Source Current vs Output High Voltage for Different Temperature (T_A) for V_CC = 1.65 V

Figure 13. I/O Source Current vs Output High Voltage for Different Temperature (T_A) for V_CC = 2.5 V

Figure 15. I/O Source Current vs Output High Voltage for Different Temperature (T_A) for V_CC = 5 V

Figure 17. V_CC – V_OH Voltage vs Temperature for Different V_CC

Figure 2. Standby Supply Current vs Temperature for Different Supply Voltage (V_CC)

Figure 4. I/O Sink Current vs Output Low Voltage for Different Temperature (T_A) for V_CC = 1.65 V

Figure 6. I/O Sink Current vs Output Low Voltage for Different Temperature (T_A) for V_CC = 2.5 V

Figure 8. I/O Sink Current vs Output Low Voltage for Different Temperature (T_A) for V_CC = 5 V

Figure 10. II/O Low Voltage vs Temperature for Different V_CC and I_OL

Figure 12. I/O Source Current vs Output High Voltage for Different Temperature (T_A) for V_CC = 1.8 V

Figure 14. I/O Source Current vs Output High Voltage for Different Temperature (T_A) for V_CC = 3.3 V

Figure 16. I/O Source Current vs Output High Voltage for Different Temperature (T_A) for V_CC = 5.5 V

Figure 18. Δ I_CC vs Temperature for Different V_CC (V_I = V_CC – 0.6 V)