SFFS055 March 2021 SN65HVD1780 , SN65HVD1781 , SN65HVD1782
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This document contains information for SN65HVD1780, SN65HVD1781, and SN65HVD1782 (SOIC and PDIP package) to aid in a functional safety system design. Information provided are:
Figure 1-1 shows the device functional block diagram for reference.
SN65HVD1780, SN65HVD1781, and SN65HVD1782 were developed using a quality-managed development process, but were not developed in accordance with the IEC 61508 or ISO 26262 standards.
This section provides Functional Safety Failure In Time (FIT) rates for SN65HVD1780, SN65HVD1781, and SN65HVD1782 based on two different industry-wide used reliability standards:
FIT IEC TR 62380 / ISO 26262 | FIT (Failures Per 109 Hours) 8-pin SOIC (D) JEDEC high-K model | FIT (Failures Per 109 Hours) 8-pin PDIP (P) JEDEC high-K model | FIT (Failures Per 109 Hours) 8-pin SOIC (D) JEDEC low-K model | FIT (Failures Per 109 Hours) 8-pin PDIP (P) JEDEC low-K model |
---|---|---|---|---|
Total Component FIT Rate | 19 | 27 | 13 | 23 |
Die FIT Rate | 10 | 5 | 5 | 3 |
Package FIT Rate | 9 | 22 | 9 | 20 |
FIT IEC TR 62380 / ISO 26262 | FIT (Failures Per 109 Hours) 8-pin SOIC (D) JEDEC high-K model | FIT (Failures Per 109 Hours) 8-pin PDIP (P) JEDEC high-K model | FIT (Failures Per 109 Hours) 8-pin SOIC (D) JEDEC low-K model | FIT (Failures Per 109 Hours) 8-pin PDIP (P) JEDEC low-K model |
---|---|---|---|---|
Total Component FIT Rate | 20 | 27 | 14 | 23 |
Die FIT Rate | 11 | 5 | 6 | 3 |
Package FIT Rate | 9 | 22 | 8 | 20 |
FIT IEC TR 62380 / ISO 26262 | FIT (Failures Per 109 Hours) 8-pin SOIC (D) JEDEC high-K model | FIT (Failures Per 109 Hours) 8-pin PDIP (P) JEDEC high-K model | FIT (Failures Per 109 Hours) 8-pin SOIC (D) JEDEC low-K model | FIT (Failures Per 109 Hours) 8-pin PDIP (P) JEDEC low-K model |
---|---|---|---|---|
Total Component FIT Rate | 26 | 30 | 16 | 25 |
Die FIT Rate | 16 | 7 | 7 | 4 |
Package FIT Rate | 10 | 23 | 9 | 21 |
The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:
Table | Category | Reference FIT Rate | Reference Virtual TJ |
---|---|---|---|
5 | CMOS, BICMO Digital analog / mixed |
25 FIT | 55°C |
The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-4 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.
The failure mode distribution estimation for SN65HVD1780, SN65HVD1781, and SN65HVD1782 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
Die Failure Modes | Failure Mode Distribution (%) |
---|---|
Receiver fail | 15% |
Transmitter fail | 63% |
I/O | 12% |
PCU | 10% |
This section provides a Failure Mode Analysis (FMA) for the pins of the SN65HVD1780, SN65HVD1781, and SN65HVD1782. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Class | Failure Effects |
---|---|
A | Potential device damage that affects functionality |
B | No device damage, but loss of functionality |
C | No device damage, but performance degradation |
D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the SN65HVD1780, SN65HVD1781, and SN65HVD1782 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the SN65HVD1780, SN65HVD1781, and SN65HVD1782 datasheet.
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
R | 1 | Host unable to receive data from bus via transceiver. Increased output current and ICC when the output state is high. | B |
RE | 2 | Receiver output always enabled. | D |
DE | 3 | Driver output always disabled. | B |
D | 4 | Host unable to transmit data to bus via transceiver. Output state is low when the driver is enabled. | B |
GND | 5 | Intended operation. | D |
A | 6 | Non-inverting signal stuck low; bus unable to reach differential high level. Communication errors likely. | B |
B | 7 | Inverting signal stuck low; bus unable to reach differential high level. Communication errors likely. | B |
VCC | 8 | Device unpowered; neither transmit nor receive functionality available. Large current load on the external VCC regulator. | B |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
R | 1 | Host unable to receive data from the bus via transceiver | B |
RE | 2 | Receiver output always disabled. | B |
DE | 3 | Driver output always disabled. | B |
D | 4 | Host unable to transmit data to the bus via transceiver. Output state is indeterminate when the driver is enabled. | B |
GND | 5 | Device unpowered; neither transmit nor receive functionality available. | B |
A | 6 | Communication errors likely; may work with degraded margin if the bus termination is not implemented. | B |
B | 7 | Communication errors likely; may work with degraded margin if the bus termination is not implemented. | B |
VCC | 8 | Device unpowered; neither transmit nor receive functionality available. | B |
Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|---|
R | 1 | RE | Undetermined state of shared net; receive functionality unlikely to work. | B |
RE | 2 | DE | Receiver is enabled when driver is disabled, and the driver is enabled when the receiver is disabled. Transceiver state may not be well-defined when this short results in contention between two active control lines from the host. | B |
DE | 3 | D | Driver output can only be output-high or disabled (high-Z). State may not be well-defined due to contention between host control lines. | B |
GND | 5 | A | Non-inverting signal stuck low; bus unable to reach differential high level. Communication errors likely. | B |
A | 6 | B | Bus unable to reach differential-high or differential-low states; communication cannot occur on bus. | B |
B | 7 | VCC | Inverting signal stuck high; bus unable to reach differential high level. Communication errors likely. | B |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
R | 1 | Host unable to receive data from bus via transceiver. Increased input current when the output state is low. | B |
RE | 2 | Receiver output always disabled. | B |
DE | 3 | Driver output always enabled. | D |
D | 4 | Host unable to transmit data to bus via transceiver. Output state is high when driver is enabled. | B |
GND | 5 | Device unpowered; neither transmit nor receive functionality available. Large current load on the external VCC regulator. | B |
A | 6 | Non-inverting signal stuck high; bus unable to reach differential high level. Communication errors likely. | B |
B | 7 | Inverting signal stuck high; bus unable to reach differential high level. Communication errors likely. | B |
VCC | 8 | Intended operation | D |