The TMDS171 is a digital video interface (DVI) or high-definition multimedia interface (HDMI) retimer. The TMDS171 supports four TMDS channels, Audio Return Channel (SPDIF_IN/ARC_OUT), Hot Plug Detect (HPD) and Digital Display Control (DDC) interfaces. The TMDS171 supports signaling rates up to 3.4 Gbps to allow for the highest resolutions of 4k2k30p 24 bits per pixel and up to WUXGA 12-bit color depth or 1080p with higher refresh rates. The TMDS171 automatically configures itself as a re-driver at low data rate (< 1 Gbps) or as a re-timer above this data rate.
The TMDS171 supports dual power supply rails of 1.2 V on VDD and 3.3 V on VCC for active power reduction. Several methods of power management are implemented to reduce overall power consumption. TMDS171 supports fixed EQ gain or adaptive EQ control by I2C or pin strap to compensate for different lengths input cable or board traces.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TMDS171 | (VQFN) 48 Pins | 7.00 mm x 7.00 mm |
TMDS171I |
Simplified Schematic![]() |
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Changes from D Revision (August 2016) to E Revision
Changes from C Revision (April 2016) to D Revision
Changes from B Revision (February 2016) to C Revision
Changes from A Revision (December 2015) to B Revision
Changes from * Revision (October 2015) to A Revision
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
VCC | 13, 43 | P | 3.3 V Power Supply |
VDD | 14, 23, 24, 37, 48 | P | 1.2 V Power Supply |
GND | 7, 19, 41, 30 | G | Ground |
Thermal Pad | G | Ground | |
MAIN LINK INPUT PINS (FAIL SAFE) | |||
IN_D2p/n | 2, 3 | I | Channel 2 Differential Input |
IN_D1p/n | 5, 6 | I | Channel 1 Differential Input |
IN_D0p/n | 8, 9 | I | Channel 0 Differential Input |
IN_CLKp/n | 11, 12 | I | Clock Differential Input |
MAIN LINK OUTPUT PINS (FAIL SAFE) | |||
OUT_D2n/p | 34, 35 | O | TMDS Data 2 Differential Output |
OUT_D1n/p | 31, 32 | O | TMDS Data 1 Differential Output |
OUT_D0n/p | 28, 29 | O | TMDS Data 0 Differential Output |
OUT_CLKn/p | 25, 26 | O | TMDS Clock Differential Output |
HOT PLUG DETECT PINS | |||
HPD_SRC | 4 | O | Hot Plug Detect Output to source side |
HPD_SNK | 33 | I | Hot Plug Detect Input from sink side |
AUDIO RETURN CHANNEL and DDC PINS | |||
SPDIF_IN | 45 | I | SPDIF signal input |
ARC_OUT | 44 | O | Audio return channel output |
SDA_SRC | 47 | I/O | Source Side TMDS Port Bidirectional DDC Data line |
SCL_SRC | 46 | I/O | Source Side TMDS Port Bidirectional DDC Clock line |
SDA_SNK, | 39 | I/O | Sink Side TMDS Port Bidirectional DDC Data Line |
SCL_SNK | 38 | I/O | Sink Side TMDS Port Bidirectional DDC Clock Line |
CONTROL PINS(2) | |||
OE | 42 | I | Operation Enable/Reset Pin OE = L: Power Down Mode OE = H: Normal Operation Internal weak pull up: Resets device when transitions from H to L |
SIG_EN | 17 | I | Signal detector circuit enable SIG_EN = L: Signal Detect Circuit Disabled: Term resistors always connected (Default) SIG_EN = H: Signal Detect Circuit Enabled: When no valid clock device enters Standby Mode. Internal weak pull down |
PRE_SEL | 20 | I 3-Level |
De-emphasis Control when I2C_EN/PIN = Low. PRE_SEL = L: -2 dB PRE_SEL = No Connect: 0 dB PRE_SEL = H: Reserved When I2C_EN/PIN = High; De-emphasis is controlled through I2C |
EQ_SEL/A0 | 21 | I | Input Receive Equalization pin strap when I2C_EN/PIN = Low EQ_SEL = L: Fixed EQ at 7.5 dB EQ_SEL = No Connect: Adaptive EQ EQ_SEL = H: Fixed at 14 dB When I2C_EN/PIN = High Address Bit 1 Note: 3 level for pin strap programming but 2 level when I2C address |
I2C_EN/PIN | 10 | I | I2C_EN/PIN = High; Puts Device into I2C Control Mode I2C_EN/PIN = Low; Puts Device into Pin Strap Mode |
SCL_CTL | 15 | I/O | I2C Clock Signal when I2C_EN/PIN = High. Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be changed by I2C |
SDA_CTL | 16 | I/O | I2C Data Signal when I2C_EN/PIN = High Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be changed by I2C |
VSadj | 22 | I | TMDS Output Voltage Swing Control; Nominal 7.06 kΩ Resistor to GND |
A1 | 27 | I | High address bit 2 for I2C programming Weak internal pull down. Note: When I2C_EN/PIN = Low for Pin Strapping Mode leave this pin as No connect |
TX_TERM_CTL | 36 | I 3-Level |
Transmit Termination Control TX_TERM_CTL = H: No transmit Termination TX_TERM_CTL = L: Reserved TX_TERM_CTL = No Connect: Automatically selects the termination impedance 2 Gbps > DR ≤ 3.4 Gbps – 150 - 300 Ω differential near end termination DR < 2 Gbps – no termination Note: If left floating; the device will be in Automatic Select Mode. DR stands for Data Rate |
SWAP/POL | 1 | I 3-Level |
Receive Polarity Swap and Receive Lane Swap control pin SWAP/POL = H: Receive Lanes Polarity Swap (Retimer Mode Only) SWAP/POL = L: Receive Lanes (Retimer and Redriver Mode) Swap SWAP/POL = No Connect, Normal Operation |
NC | 18, 40 | – | No connect |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply Voltage Range | VCC | –0.3 | 4 | V |
VDD | –0.3 | 1.4 | ||
Voltage Range | Main Link Input Differential Voltage (IN_Dx, IN_CLKx); IIN = 15mA | VCC - 0.75 V | VCC + 0.3 V | |
TMDS Outpus ( OUT_Dx) | –0.3 | 4 | ||
HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, A1, PRE_SEL, EQ_SEL/A0, I2C_EN/PIN, SIG_EN, TX_TERM_CTL, | –0.3 | 4 | ||
HDP_SNK, SDA_SNK, SCL_SNK, SDA_SRC, SCL_SRC | –0.3 | 6 | ||
Input Current IIN | Main Link Input Differential Voltage (IN_Dx, IN_CLKx); | 15 | mA | |
Continuous power dissipation | See Thermal Information | |||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply Voltage Nominal Value 3.3 V | 3.135 | 3.3 | 3.465 | V | |
VDD | Supply Voltage Nominial Value 1.2 V | 1.1 | 1.2 | 1.27 | V | |
TSTG | Storage temperature | –65 | 150 | °C | ||
TCASE | Case temperature | 92.7 | °C | |||
TA | Operating free-air temperature (TMDS171) | 0 | 85 | °C | ||
Operating free-air temperature (TMDS171I) | –40 | 85 | °C | |||
MAIN LINK DIFFERENTIAL PINS | ||||||
VID(PP) | Peak-to-peak input differential voltage | 75 | 1560 | mVpp | ||
VIC | Input Common Mode Voltage | VCC – 0.4 | VCC + 0.1 | V | ||
dR | Data rate | 0.25 | 3.4 | Gbps | ||
R(VSADJ) | TMDS compliant swing voltage bias resistor 1% | 7.06 | KΩ | |||
CONTROL PINS | ||||||
VI(DC) | DC Input Voltage | –0.3 | 3.6 | V | ||
VIL(1) | Low-level input voltage OE | 0.8 | V | |||
Low-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL pins only(1) | 0.3 | V | ||||
VIM(1) | Mid-Level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL pins only(1) | 1 | 1.2 | 1.4 | V | |
VIH(1) | High-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL, OE(2) pins only(1) | 2.6 | V | |||
VOL | Low-level output voltage | 0.4 | V | |||
VOH | High-level output voltage | 2.4 | V | |||
IIH | High level input current | 30 | 30 | µA | ||
IIL | Low level input current | –25 | 25 | µA | ||
IOS | Short circuit output current | –50 | 50 | mA | ||
IOZ | High impedance output current | 10 | µA | |||
R(OEPU) | Pull up resistance on OE pin | 150 | 250 | KΩ |
THERMAL METRIC(1) | RGZ (QFN) | UNIT | |
---|---|---|---|
48 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 31.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 18.2 | |
RθJB | Junction-to-board thermal resistance | 8.1 | |
ψJT | Junction-to-top characterization parameter | 0.4 | |
ψJB | Junction-to-board characterization parameter | 8.1 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.2 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Power Supply | |||||||
P(D1)(1)(2) | Device power Dissipation (Retimer Operation) | OE = H, VCC = 3.3 V / 3.465 V, VDD = 1.2 V / 1.27 V IN_Dx: VID_PP = 1200 mV, I2C_EN/PIN = L, PRE_SEL= H, EQ_CTL= H, SDA_CTL/CLK_CTL = 0 V 3.4 Gbps TMDS pattern, VI = 3.3 V; VSADJ = 7.06 kΩ |
675 | 875 | mW | ||
P(D2)(1)(2) | Device power Dissipation (Redriver Operation) | 400 | 600 | mW | |||
P(SD1)(1)(2)(3) | Device power in Standby | OE = H, VCC = 3.3 V / 3.465 V VDD = 1.2 V / 1.27 V , HPD = H, No Valid input Signal |
50 | 100 | mW | ||
P(SD2)(1)(2)(3) | Device power in PowerDown | OE = L, VCC = 3.3 V / 3.465 V VDD = 1.2 V / 1.27 V |
10 | 30 | mW | ||
ICC1(1)(2) | VCC Supply current (TMDS 3.4 Gpbs Retimer Mode) | OE = H, VCC = 3.3 V / 3.465 V VDD = 1.2 V / 1.27 V IN_Dx: VID_PP = 1200 mV, 3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H |
80 | 140 | mA | ||
IDD1(1)(2) | VDD Supply current (TMDS 3.4 Gpbs Retimer Mode) | 286 | 325 | mA | |||
ICC2(1)(2) | VCC Supply current (TMDS 3.4 Gpbs Redriver Mode) | OE = H, VCC = 3.3 V / 3.465 V VDD = 1.2 V / 1.27 V IN_Dx: VID_PP = 1200 mV, 3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H, SDA_CTL/CLK_CTL = 0V, SLEW_CTL = H |
51 | mA | |||
IDD2(1)(2) | VDD Supply current (TMDS 3.4 Gpbs Redriver Mode) | 188 | mA | ||||
I(SD1)(3) | Standby current | OE = H, VCC = 3.3 V / 3.465 V VDD = 1.2 V / 1.27 V HPD = H: No valid signal on IN_CLK |
3.3V Rail(1) | 6 | 15 | mA | |
1.2V Rail | 40 | 50 | |||||
I(SD2)(3) | PowerDown current | OE = L, VCC = 3.3 V / 3.465 V VDD = 1.2 V / 1.27 V |
3.3V Rail(1) | 2 | 5 | mA | |
1.2V Rail | 3.5 | 15 | |||||
TMDS Differential Input | |||||||
D(R_RX_DATA) | TMDS data lanes data rate | 0.25 | 3.4 | Gbps | |||
D(R_RX_CLK) | TMDS clock lanes clock rate | 25 | 340 | MHz | |||
tRX_DUTY | Input clock duty circle | 40% | 50% | 60% | |||
tCLK_JIT | Input clock jitter tolerance | 0.3 | Tbit | ||||
tDATA_JIT | Input data jitter tolerance | Test the TTP2 See Figure 11 | 150 | ps | |||
tRX_INTRA | Input intra-pair skew tolerance | Test at TTP2 when DR = 1.6 Gbps See Figure 11 | 112 | ps | |||
tRX_INTER | Input inter-pair skew tolerance | 1.8 | ns | ||||
EQH(D) | Fixed EQ gain for data lane IN_D(0,1,2)n/p | EQ_SEL/A0=H; Fixed EQ gain, test at 3.4 Gbps | 14 | dB | |||
EQL(D) | Fixed EQ gain for data lane IN_D(0,1,2)n/p | EQ_SEL/A0=L; Fixed EQ gain, test at 3.4 Gbps | 7.5 | ||||
EQZ(D) | Adaptive EQ gain for data lane IN_D(0,1,2)n/p | EQ_SEL/A0=NC; adaptive EQ | 2 | 14 | |||
EQ(C) | EQ gain for clock lane IN_CLKn/p | EQ_SEL/A0=H,LNC | 0 | ||||
R(INT) | Input differential termination impedance | 90 | 100 | 115 | Ω | ||
TMDS Differential Output | |||||||
VOH | Single-ended high level output voltage | PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ | VCC - 10mV | VCC + 10mV | V | ||
PRE_SEL = NC; TX_TERM_CTL = H; OE = NC; DR = 2.97 Gbps; VSadj = 7.06 kΩ | VCC - 200mV | VCC + 10mV | |||||
VOL | Single-ended low level output voltage No Pre-emphasis, Load is 50 Ω pull ups to 3.135 V and 3.465 V | PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ | VCC - 600mV | VCC - 400mV | |||
PRE_SEL = NC; TX_TERM_CTL = H; OE = NC; DR = 2.97 Gbps; VSadj = 7.06 kΩ | VCC - 700mV | VCC - 400mV | |||||
V(SWING_DA) | Single-ended output voltage swing on data lane | PRE_SEL = NC; TX_TERM_CTL = H/NC; OE = NC; DR = ≤ 3.4 Gbps; VSadj = 7.06 kΩ |
400 | 500 | 600 | mV | |
V(SWING_CLK) | Single-ended output voltage swing on clock lane | PRE_SEL = NC; TX_TERM_CTL = H/NC; OE = NC; DR = ≤ 3.4 Gbps; VSadj = 7.06 kΩ |
400 | 500 | 600 | ||
ΔV(SWING) | Change in single-end output voltage swing per 100Ω ΔVSadj | 20 | |||||
ΔVOCM(SS) | Change in steady state output common mode voltage between logic levels | –5 | 5 | ||||
VOD(PP) | Initial output differential voltage before steady state when pre-emphasis or de-emphasis is implemented | VSadj = 7.06 kΩ; PRE_SEL = NC, See Figure 8 | 800 | 1200 | |||
VOD(SS) | Steady state output differential voltage | VSadj = 7.06 kΩ; PRE_SEL = L, See Figure 9 | 600 | 1075 | |||
IOS | Short circuit current limit | Main link output shorted to GND | 50 | mA | |||
ILEAK | Failsafe condition leakage current | VCC = 0 V; VDD = 0 V; TMDS Outputs pulled to 3.3V through 50 Ω resistor | 45 | µA | |||
R(TERM) | Source Termination resistance | 150 | 300 | Ω | |||
DDC and I2C | |||||||
VI-DC | SCL/SDA_SNK, SCL/SDA_SRC DC input voltage | –0.3 | 5.5 | V | |||
SCL/SDA_CTL, DC input voltage | –0.3 | 3.6 | V | ||||
VIL | SCL/SDA_SNK, SCL/SDA_SRC Low level input voltage | 0.3 x VCC | V | ||||
SCL/SDA_CTL Low level input voltage | 0.3 x VCC | V | |||||
VIH | SCL/SDA_SNK, SCL/SDA_SRC high level input voltage | 3 | V | ||||
SCL/SDA_CTL high level input voltage | 0.7 x VCC | V | |||||
VOL | SCL/SDA_CTL, SCL/SDA_SRC low level output voltage | IO = 3 mA and VCC > 2 V | 0.4 | V | |||
IO = 3 mA and VCC < 2 V | 0.2 x VCC | V | |||||
fSCL | SCL clock frequency fast I2C mode for local I2C control | 400 | kHz | ||||
Cbus | Total capacitive load for each bus line (DDC and local I2C pins) | 400 | pF | ||||
HPD | |||||||
VIH | High-level input voltage | HPD_SNK | 2.1 | V | |||
VIL | Low-level input voltage | HPD_SNK | 0.8 | ||||
VOH | High-level output voltage | IOH = -500 µA; HPD_SRC | 2.4 | 3.6 | |||
VOL | Low-level output voltage | IOL = -500 µA; HPD_SRC | 0 | 0.1 | |||
ILEAK | Failsafe condition leakage current | VCC = 0 V; VDD = 0 V; HPD_SNK = 5 V | 40 | ||||
IH(HPD) | High level input current | Device powered; VIH = 5 V; IH(HPD) includes Rpd(HPD) resistor current | 40 | µA | |||
Device powered; VIL = 0.8 V; IH(HPD) includes Rpd(HPD) resistor current | 30 | ||||||
Rpd(HPD) | HPD input termination to GND; | VCC < 0 V | 150 | 190 | 220 | kΩ | |
SPDIF and ARC | |||||||
V(EL) | Operating DC voltage for single mode ARC output | Test at ARC_OUT, see Figure 19 | 0 | 5 | V | ||
VIN(DC) | Operating DC voltage for SPDIF input | 0.05 | V | ||||
V(SP_SW) | Signal amplitude of SPDIF input | 0.2 | 0.5 | 0.6 | V | ||
V(ElSWING) | Signal amplitude on the ARC output | Test at ARC_OUT, 75 Ω external termination resistor, see Figure 19 | 0.4 | 0.5 | 0.6 | V | |
CLK(ARC) | Signal frequency on ARC | Test at ARC_OUT, see Figure 19 | 3.687 | 5.645±0.1% | 13.517 | MHz | |
Duty Cycle | Output Clock Duty cycle | 45% | 50% | 55% | |||
Data Rate | SPDIF Input DR | 7.373 | 11.29 | 27.034 | Mbps | ||
tEDGE | The rise/fall time for ARC output | From 10% to 90% voltage level, see Figure 19 | 0.4 | UI | |||
R(IN_SPDIF) | The Input Termination resistance for SPDIF | 75 | Ω | ||||
R(EST) | Single mode Output Termination resistance | 0.1 MHz to 128 times the maximum frame rate | 36 | 55 | 75 | Ω |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
TMDS Redriver Mode | ||||||
DR | Data rate (Redriver mode) | 250 | 3400 | Mbps | ||
tPLH | Propagation delay time (low to high) | 250 | 600 | ps | ||
tPHL | Propagation delay time (high to low) | 250 | 800 | |||
tT1 | Transition time (rise and fall time); measured at 20% and 80% levels for Data Lanes. | TX_TERM_CTL=L; PRE_SEL=NC; Data Rate 3.4 Gbps; Clock 340 MHz | 75 | |||
tSK1(T) | Intra-pair output skew | TX_TERM_CTL=NC; PRE_SEL=NC; | 40 | |||
tSK2(T) | Inter-pair output skew | TX_TERM_CTL=NC; PRE_SEL=NC; | 100 | |||
tJITD1 | Total output data jitter | DR = 750 Mbps, PRE_SEL = NC, EQ_SEL/A0 = NC. See Figure 5 at TTP3 | 0.2 | Tbit | ||
tJITC1 | Total output clock jitter | 0.25 | ||||
TMDS Retimer Mode | ||||||
DR | Data rate (retimer mod ) | 1.2 | 3.4 | Gbps | ||
d(XVR) | Automatic redriver to Retimer Cross-Over | Measured with input signal applied from 0 to 200 mVPP | 0.75 | 1.00 | 1.25 | Gbps |
f(CROSSOVER) | Crossover frequency hysteresis | 250 | MHz | |||
PLL(BW) | Data Retimer PLL bandwidth | Default loop bandwidth setting | 0.4 | 1 | MHz | |
tACQ | Input Clock Frequency Detection and Retimer Acquisition Time | 180 | µs | |||
IJT1 | Input Clock Jitter Tolerance | Tested when data rate > 1.0 Gbps | 0.3 | Tbit | ||
tT1 | Transition time (rise and fall time); measured at 20% and 80% levels for Data Lanes. TMDS | 75 | ps | |||
tDCD | OUT_CLK ± duty cycle | 40% | 50% | 60% | ||
tSK_INTER | Inter-pair output skew | Default setting for internal inter-pair skew adjust, PRE_SEL = NC; TX_TERM_CTL = NC, DR ≤ 3.4 Gbps; See Figure 6 | 0.2 | Tch | ||
tSK_INTRA | Intra-pair output skew | Default setting for internal intra-pair skew adjust, PRE_SEL = NC; TX_TERM_CTL = NC, DR ≤ 3.4 Gbps; See Figure 6 | 0.15 | Tbit | ||
tJITC2 | Total output clock jitter | CLK Rate ≤ 340 MHz | 0.25 | Tbit | ||
tJITD2 | Total output data jitter | DR ≤ 3.4 Gbps; See Figure 11 | 0.2 | Tbit | ||
HPD | ||||||
tPD(HPD) | Propagation delay from HPD_SNK to HPD_SRC; rising edge and falling edge(1) | see Figure 13; not valid during switching time | 40 | 120 | ns | |
tT(HPD) | HPD logical disconnected timeout | see Figure 14 | 2 | ms | ||
DDC and I2C | ||||||
tr | Rise time of both SDA and SCL signals | VCC = 3.3 V | 300 | ns | ||
tf | Fall time of both SDA and SCL signals | 300 | ||||
tHIGH | Pulse duration, SCL high | 0.6 | µs | |||
tLOW | Pulse duration, SCL low | 1.3 | ||||
tSU1 | Setup time, SDA to SCL | 100 | ns | |||
tST,STA | Setup time, SCL to start condition | 0.6 | µs | |||
tHD,STA | Hold time, start condition to SCL | 0.6 | ||||
tST,STO | Setup time, SCL to stop condition | 0.6 | ||||
t(BUF) | Bus free time between stop and start condition | 1.3 | ||||
tPLH1 | Propagation delay time, low-to-high-level output | Source to Sink:100 kbps pattern; Cb(Sink) = 400 pF(2); see Figure 17 |
360 | ns | ||
tPHL1 | Propagation delay time, high-to-low-level output | 230 | ||||
tPLH2 | Propagation delay time, low-to-high-level output | Sink to Source: 100 kbps pattern; Cb(Source) = 100 pF(2); see Figure 18 |
250 | |||
tPHL2 | Propagation delay time, high-to-low-level output | 200 |