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  • TUSB320LAI, TUSB320HAI USB Type-C Configuration Channel Logic and Port Control

    • SLLSEQ8D October   2015  – May 2017 TUSB320HAI , TUSB320LAI

      PRODUCTION DATA.  

  • CONTENTS
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  • TUSB320LAI, TUSB320HAI USB Type-C Configuration Channel Logic and Port Control
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Cables, Adapters, and Direct Connect Devices
        1. 7.1.1.1 USB Type-C Receptacles and Plugs
        2. 7.1.1.2 USB Type-C Cables
        3. 7.1.1.3 Legacy Cables and Adapters
        4. 7.1.1.4 Direct Connect Devices
        5. 7.1.1.5 Audio Adapters
    2. 7.2 Feature Description
      1. 7.2.1 Port Role Configuration
        1. 7.2.1.1 Downstream Facing Port (DFP) - Source
        2. 7.2.1.2 Upstream Facing Port (UFP) - Sink
        3. 7.2.1.3 Dual Role Port (DRP)
      2. 7.2.2 Type-C Current Mode
      3. 7.2.3 Accessory Support
        1. 7.2.3.1 Audio Accessory
        2. 7.2.3.2 Debug Accessory
      4. 7.2.4 I2C and GPIO Control
      5. 7.2.5 VBUS Detection
    3. 7.3 Device Functional Modes
      1. 7.3.1 Unattached Mode
      2. 7.3.2 Active Mode
      3. 7.3.3 Dead Battery Mode
      4. 7.3.4 Shutdown Mode
    4. 7.4 Programming
    5. 7.5 Register Maps
      1. 7.5.1 CSR Registers (address = 0x00 - 0x07)
      2. 7.5.2 CSR Registers (address = 0x08)
      3. 7.5.3 CSR Registers (address = 0x09)
      4. 7.5.4 CSR Registers (address = 0x0A)
      5. 7.5.5 CSR Registers (address = 0x45)
      6. 7.5.6 CSR Registers (address = 0xA0)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DRP in I2C Mode
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DFP in I2C Mode
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 UFP in I2C Mode
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 Initialization Setup
      1. 8.3.1 TUSB320LA Initialization Procedure
      2. 8.3.2 TUSB320HA Initialization Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE
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DATA SHEET

TUSB320LAI, TUSB320HAI USB Type-C Configuration Channel Logic and Port Control

1 Features

  • USB Type-C™ Specification 1.1
  • Backward Compatible with USB Type-C Specification 1.0
  • Supports Up to 3 A of Current Advertisement and Detection
  • Mode Configuration
    • Host Only – DFP (Source)
    • Device Only – UFP (Sink)
    • Dual Role Port – DRP
    • Supports both Try.SRC and Try.SNK
  • Channel Configuration (CC)
    • Attach of USB Port Detection
    • Cable Orientation Detection
    • Role Detection
    • Type-C Current Mode (Default, Medium, High)
  • VBUS Detection
  • I2C or GPIO Control
  • Supports up to 400 kHz I2C
  • Role Configuration Control Through I2C
  • Supply Voltage: 2.7 V to 5 V
  • Low Current Consumption
  • Industrial Temperature Range of –40 to 85°C

2 Applications

  • Host, Device, Dual Role Port Applications
  • Mobile Phones
  • Tablets and Notebooks
  • USB Peripherals

3 Description

The TUSB320LA and TUSB320HA devices, hereafter called TUSB320 unless otherwise noted, are Texas Instrument's third generation Type-C configuration channel logic and port controller. The TUSB320 devices use the CC pins to determine port attach and detach, cable orientation, role detection, and port control for Type-C current mode. The TUSB320 devices can be configured as a downstream facing port (DFP), upstream facing port (UFP) or a dual role port (DRP) making them ideal for any application.

The TUSB320 devices have an alternate configuration as a DFP or UFP according to the Type-C specifications. The CC logic block monitors the CC1 and CC2 pins for pullup or pulldown resistances to determine when a USB port has been attached, the orientation of the cable, and the role detected. The CC logic detects the Type-C current mode as default, medium, or high depending on the role detected. VBUS detection is implemented to determine a successful attach in UFP and DRP modes.

The devices operate over a wide supply range and have low-power consumption. The TUSB320 is available in two versions of enable: Active low enable called TUSB320LA and active high enable called TUSB320HA. The TUSB320 family of devices are available in industrial temperature ranges.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TUSB320LAI X2QFN (12) 1.60 mm × 1.60 mm
TUSB320HAI X2QFN (12) 1.60 mm × 1.60 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

TUSB320LAI TUSB320HAI fp_bd_sllsen9_320.gif

Sample Applications

TUSB320LAI TUSB320HAI fp_image_sllsen9_320.png

4 Revision History

Changes from C Revision (October 2016) to D Revision

  • Changed RVBUS values From: MIN = 891, TYP = 900, MAX = 909 KΩ To: MIN = 855, TYP = 887, MAX = 920 KΩ Go

Changes from B Revision (September 2016) to C Revision

  • Changed text for Pin 7 in the Pin Functions table From: "default current mode detected (H); medium or high current mode detected (L)." To: "Refer to Table 3 for more details." Go
  • Changed text for Pin 8 in the Pin Functions table From: "default or medium current mode detected (H); high current mode detected (L)." To: "Refer to Table 3 for more details." Go

Changes from A Revision (March 2016) to B Revision

  • Changed pins CC1 and CC2 values From: MIN = –0.3 MAX = VDD + 0.3 To: MIN –0.3 MAX = 6 in the Absolute Maximum RatingsGo

Changes from * Revision (October 2015) to A Revision

  • Added Note 1 and 2 to the Pin Functions tableGo
  • Changed the DESCRIPTION of pin EN_N pin in the Pin Functions tableGo
  • Changed the DESCRIPTION of pin EN pin in the Pin Functions tableGo
  • Changed the DESCRIPTION of pin VDD in the Pin Functions tableGo
  • Added Test Condition "See Figure 1" to VBUS_THR in the Electrical Characteristics Go
  • Added Note 2 to the Electrical Characteristics table Go
  • Changed the last sentence of the Debug Accessory sectionGo
  • Added Note: "SW must make sure..." to the Description of INTERRUPT_STATUS in Table 9 Go
  • Added text to list item 2 in the TUSB320LA Initialization Procedure sectionGo
  • Added text to list item 2 in the TUSB320HA Initialization Procedure sectionGo

5 Pin Configuration and Functions

RWB Package
12-Pin X2QFN
TUSB320LA Top View
TUSB320LAI TUSB320HAI po_sllsen9_320.gif
RWB Package
12-Pin X2QFN
TUSB320HA Top View
TUSB320LAI TUSB320HAI po_sllsep2_320H.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME TUSB320LA TUSB320HA
CC1 1 1 I/O Type-C configuration channel signal 1
CC2 2 2 I/O Type-C configuration channel signal 2
PORT(1) 3 3 I Tri-level input pin to indicate port mode. The state of this pin is sampled when EN_N is asserted low in the TUSB320L device, EN is asserted high in the TUSB320H device, and VDD is active. This pin is also sampled following a I2C_SOFT_RESET.
H - DFP (Pull-up to VDD if DFP mode is desired)
NC - DRP (Leave unconnected if DRP mode is desired)
L - UFP (Pull-down or tie to GND if UFP mode is desired)
VBUS_DET(1) 4 4 I 5-V to 28-V VBUS input voltage. VBUS detection determines UFP attachment. One 900-kΩ external resistor required between system VBUS and VBUS_DET pin.
ADDR(1) 5 5 I Tri-level input pin to indicate I2C address or GPIO mode:
H — I2C is enabled and I2C 7-bit address is 0x67.
NC — GPIO mode (I2C is disabled)
L — I2C is enabled and I2C 7-bit address is 0x47.
ADDR pin should be pulled up to VDD if high configuration is desired
INT_N/OUT3(1) 6 6 O The INT_N/OUT3 is a dual-function pin. When used as the INT_N, the pin is an open drain output in I2C control mode and is an active low interrupt signal for indicating changes in I2C registers. When used as OUT3, the pin is in audio accessory detect in GPIO mode: no detection (H), audio accessory connection detected (L).
SDA/OUT1(1)(2) 7 7 I/O The SDA/OUT1 is a dual-function pin. When I2C is enabled (ADDR pin is high or low), this pin is the I2C communication data signal. When in GPIO mode (ADDR pin is NC), this pin is an open drain output for communicating Type-C current mode detect when the device is in UFP mode: Refer to Table 3 for more details.
SCL/OUT2(1)(2) 8 8 I/O The SCL/OUT2 is a dual function pin. When I2C is enabled (ADDR pin is high or low), this pin is the I2C communication clock signal. When in GPIO mode (ADDR pin is NC), this pin is an open drain output for communicating Type-C current mode detect when the device is in UFP mode: Refer to Table 3 for more details.
ID 9 9 O Open drain output; asserted low when the CC pins detect device attachment when port is a source (DFP), or dual-role (DRP) acting as source (DFP).
GND 10 10 G Ground
EN_N 11 — I Enable signal; active low. Pulled up to VDD internally to disable the TUSB320L device. If controlled externally, must be held low at least for 50 ms after VDD has reached its valid voltage level.
EN — 11 I Enable signal; active high. Pulled down to GND internally to disable the TUSB320H device. If controlled externally, must be held low at least for 50 ms after VDD has reached its valid voltage level.
VDD 12 12 P Positive supply voltage. VDD must ramp within 25 ms or less
(1) When VDD is off, the TUSB320 non-failsafe pins (VBUS_DET, ADDR, PORT, OUT[3:1] pins) could back-drive the TUSB320 device if not handled properly. When necessary to pull these pins up, it is recommended to pullup PORT, ADDR, and INT_N/OUT3 to the device VDD supply. The VBUS_DET must be pulled up to VBUS through a 900-kΩ resistor.
(2) When using the 3.3 V supply for I2C, the end user must ensure that the VDD is 3 V and above. Otherwise the I2C may back power the device.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage VDD –0.3 6 V
Control pins PORT, ADDR, ID, EN_N, INT_N/OUT3 –0.3 VDD + 0.3 V
CC1, CC2 –0.3 6
SDA/OUT1, SCL/OUT2 –0.3 VDD + 0.3
VBUS_DET , EN –0.3 4
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage range 2.7 5 V
VBUS System VBUS voltage 4 5 28 V
TA TUSB320HAI and TUSB320LAI Operating free air temperature range –40 25 85 °C

6.4 Thermal Information

THERMAL METRIC(1) TUSB320 UNIT
RWB (X2QFN)
12 PINS
RθJA Junction-to-ambient thermal resistance 169.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 68.1 °C/W
RθJB Junction-to-board thermal resistance 83.4 °C/W
ψJT Junction-to-top characterization parameter 2.2 °C/W
ψJB Junction-to-board characterization parameter 83.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and C Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER CONSUMPTION
IUNATTACHED_UFP Current consumption in unattached mode when port is unconnected and waiting for connection. [VDD = 4.5 V, EN_N (TUSB320LA) = L, EN (TUSB320HA) = H, ADDR = NC, PORT = L] 70 µA
IACTIVE_UFP Current consumption in active mode. [VDD = 4.5 V, EN_N (TUSB320LA) = L, EN (TUSB320HA) = H, ADDR = NC, PORT = L] 70 µA
ISHUTDOWN Leakage current when VDD is supplied, but the TUSB320 device is not enabled. [VDD = 4.5 V, EN_N (TUSB320LA) = H, EN (TUSB320HA) = L] 0.04 µA
CC1 AND CC2 PINS
RCC_DB Pulldown resistor when in dead-battery mode. 4.1 5.1 6.1 kΩ
RCC_D Pulldown resistor when in UFP or DRP mode. 4.6 5.1 5.6 kΩ
VUFP_CC_USB Voltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising default current source capability. 0.25 0.61 V
VUFP_CC_MED Voltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising medium (1.5-A) current source capability. 0.7 1.16 V
VUFP_CC_HIGH Voltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising high (3-A) current source capability. 1.31 2.04 V
VTH_DFP_CC_USB Voltage threshold for detecting a UFP attach when configured as a DFP and advertising default current source capability. 1.51 1.6 1.64 V
VTH_DFP_CC_MED Voltage threshold for detecting a UFP attach when configured as a DFP and advertising medium current (1.5-A) source capability. 1.51 1.6 1.64 V
VTH_DFP_CC_HIGH Voltage threshold for detecting a UFP attach when configured as a DFP and advertising high current (3.0-A) source capability. 2.46 2.6 2.74 V
ICC_DEFAULT_P Default mode pullup current source when operating in DFP or DRP mode. 64 80 96 µA
ICC_MED_P Medium (1.5-A) mode pullup current source when operating in DFP or DRP mode. 166 180 194 µA
ICC_HIGH_P High (3-A) mode pullup current source when operating in DFP or DRP mode.(1) 304 330 356 µA
CONTROL PINS: PORT, ADDR, INT/OUT3, EN_N, EN, ID
VIL Low-level control signal input voltage (PORT, ADDR, EN_N, EN) 0.4 V
VIM Mid-level control signal input voltage (PORT, ADDR) 0.28 × VDD 0.56 × VDD V
VIH High-level control signal input voltage (PORT, ADDR, EN_N) VDD – 0.3 VDD V
VIH_EN High-Level control signal input voltage for EN for TUSB320HA 1.05 3.65 V
IIH High-level input current –20 20 µA
IIL Low-level input current –10 10 µA
IID_LEAKAGE Current Leakage on ID pin VDD = 0 V; ID = 5 V 10 µA
REN_N Internal pullup resistance for EN_N for TUSB320LA 1.1 MΩ
REN Internal pulldown resistance for EN for TUSB320HA 500 kΩ
Rpu(2) Internal pullup resistance (PORT, ADDR) 588 kΩ
Rpd (2) Internal pulldown resistance (PORT, ADDR) 1.1 MΩ
VOL Low-level signal output voltage (open-drain) (INT_N/OUT3, ID) IOL = –1.6 mA 0.4 V
Rp_ODext External pullup resistor on open drain IOs (INT_N/OUT3, ID) 200 kΩ
Rp_TLext Tri-level input external pullup resistor (PORT, ADDR) 4.7 kΩ
I2C - SDA/OUT1, SCL/OUT2 CAN OPERATE FROM 1.8 V OR 3.3 V (±10%)(3)
VDD_I2C Supply range for I2C (SDA/OUT1, SCL/OUT2) 1.65 1.8 3.6 V
VIH High-level signal voltage 1.05 3.6 V
VIL Low-level signal voltage 0.4 V
VOL Low-level signal output voltage (open drain) IOL = –1.6 mA 0.4 V
VBUS_DET IO PINS (CONNECTED TO SYSTEM VBUS SIGNAL)
VBUS_THR VBUS threshold range See Figure 1 2.95 3.3 3.8 V
RVBUS External resistor between VBUS and VBUS_DET pin 855 887 920 KΩ
RVBUS_PD Internal pulldown resistance for VBUS_DET 95 KΩ
(1) VDD must be 3.5 V or greater to advertise 3 A current.
(2) Internal pullup and pulldown for PORT and ADDR are removed after the device has sampled EN = high or EN_N = low.
(3) When using 3.3 V for I2C, customer must ensure VDD is above 3.0 V at all times.

6.6 Timing Requirements

MIN NOM MAX UNIT
I2C (SDA, SCL)
tSU:DAT Data setup time 100 ns
tHD;DAT Data hold time 10 ns
tSU:STA Set-up time, SCL to start condition 0.6 µs
tHD:STA Hold time (repeated), start condition to SCL 0.6 µs
tSU:STO Set up time for stop condition 0.6 µs
tBUF Bus free time between a stop and start condition 1.3 µs
tVD;DAT Data valid time 0.9 µs
tVD;ACK Data valid acknowledge time 0.9 µs
fSCL SCL clock frequency; I2C mode for local I2C control 400 kHz
tr Rise time of both SDA and SCL signals 300 ns
tf Fall time of both SDA and SCL signals 300 ns
CBUS_100KHZ Total capacitive load for each bus line when operating at ≤ 100 kHz 400 pF
CBUS_400KHz Total capacitive load for each bus line when operating at 400 kHz 100 pF

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tCCCB_DEFAULT Power on default of CC1 and CC2 voltage debounce time DEBOUCE
register = 2'b00		 168 ms
tVBUS_DB Debounce of VBUS_DET pin after valid VBUS_THR 2 ms
tDRP_DUTY_CYCLE Power-on default of percentage of time DRP advertises DFP during a tDRP DRP_DUTY_CYCLE
register = 2'b00		 30%
tDRP The period during which the TUSB320HA or the TUSB320LA in DFP mode completes a DFP to UFP and back advertisement. 50 75 100 ms
tI2C_EN Time from TUSB320LA EN_N low or TUSB320HA EN high and VDD active to I2C access available 100 ms
tSOFT_RESET Soft reset duration 26 49 95 ms
TUSB320LAI TUSB320HAI tvbus_db_sllsen9_320.gif Figure 1. VBUS Detect and Debounce

 
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