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This document contains information for UCC28730-Q1 (SOIC (7) package) to aid in a functional safety system design. Information provided are:
Figure 1-1 shows the device functional block diagram for reference.
UCC28730-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.
This section provides Functional Safety Failure In Time (FIT) rates for UCC28730-Q1 based on two different industry-wide used reliability standards:
FIT IEC TR 62380 / ISO 26262 | FIT (Failures Per 109 Hours) |
---|---|
Total Component FIT Rate (50 mW, 100 mW, 150 mW) | 10, 11, 13 |
Die FIT Rate (50 mW, 100 mW, 150 mW) | 3, 4, 5 |
Package FIT Rate (50 mW, 100 mW, 150 mW) | 7, 7 , 8 |
The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:
Table | Category | Reference FIT Rate | Reference Virtual TJ |
---|---|---|---|
5 | CMOS,
BICMOS Digital, analog / mixed | 25 FIT | 55°C |
The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.
The failure mode distribution estimation for UCC28730-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
Die Failure Modes | Failure Mode Distribution (%) |
---|---|
DRV stuck low | 34 |
DRV stuck high | 20 |
Incorrect Vout regulation | 17 |
No effect | 29 |
This section provides a Failure Mode Analysis (FMA) for the pins of the UCC28730-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Class | Failure Effects |
---|---|
A | Potential device damage that affects functionality |
B | No device damage, but loss of functionality |
C | No device damage, but performance degradation |
D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the UCC28730-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the UCC28730-Q1 data sheet.
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
VDD | 1 | Device is not function system will not startup. | B |
VS | 2 | IC remains in input under voltage protection mode. The output of the Flyback converter remains at zero. | B |
CBC | 3 | Cable compensation will be set at its highest value. | C |
GND | 4 | No effect. | D |
CS | 5 | When CS pin is shorted before the IC start-up, CS pin short protection. The output of the Flyback converter remains at zero. | B |
When CS pin is shorted after the IC already in operation, DRV remains high. Potential power stage damage and it might cause IC damange. | A | ||
DRV | 6 | DRV remains low. The output of the Flyback converter remains at zero. | B |
N/A | 7 | ||
HV | 8 | The VDD capacitor cannot be trickle charged and the converter will never startup. | B |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
VDD | 1 | No positive supply applied to device, device is not functional. | B |
VS | 2 | IC remains in input under voltage protection mode. The output of the Flyback converter remains at zero. | B |
CBC | 3 | Cable compensation is reduced to It's minimal value. | C |
GND | 4 | Device damage | A |
CS | 5 | When CS pin is shorted before the IC start-up, CS pin short protection. The output of the Flyback converter remains at zero. | B |
When CS pin is shorted after the IC already in operation, DRV remais high. Potential power stage damage and it might cause IC damange. | A | ||
DRV | 6 | The output of the Flyback converter remains at zero. | B |
N/A | 7 | ||
HV | 8 | The VDD capacitor cannot be trickle charged. Output of the converter remains at zero volts. | B |
Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|---|
VDD | 1 | VS | VS max voltage rating exceeded, device damaged, possible Flyback switch damage | A |
VS | 2 | CBC | Cable compensation will not be stable, output voltage will not regulate correctly | C |
CBC | 3 | GND | Cable compensation will be set at its highest value. | C |
GND | 4 | N/A | ||
CS | 5 | DRV | CS max voltage rating will be exceeded, device damage, possible Flyback switch damage | A |
DRV | 6 | N/A | ||
N/A | 7 | N/A | ||
HV | 8 | N/A |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
VDD | 1 | No Effect. | D |
VS | 2 | DRV remains low. Possible IC damage. | A |
CBC | 3 | DRV remains low. Possible IC damage. | A |
GND | 4 | No positive supply applied to device. Device is non-functional. | B |
CS | 5 | DRV remains low. Possible IC damage. | A |
DRV | 6 | DRV remains high. Possible IC damage and Flyback switch damage. | A |
N/A | 7 | ||
HV | 8 | The max rating of VDD will be exceeded, possible device damage and Flyback switch damage. | A |