AM62L Power Supply Implementation

Abstract

This application note describes the AM62L power supply implementation for different use cases and low power modes. The power delivery network (PDN) in this document can be used as a guide for integrating PMIC or discrete power designs into applications using the Texas Instruments AM62L Sitara™ Processor. Example supply and digital diagrams are provided to assist the design process. For any questions or technical support needed to assist the design process, use the TI E2E™ design support forum.

Trademarks

Sitara™ and TI E2E™ are trademarks of Texas Instruments.

All trademarks are the property of their respective owners.

1 Introduction

The AM62L Arm-based processor is a low-cost, power-efficient system-on-chip (SoC) designed for a wide range of industrial and general-purpose applications. With two ARM Cortex-A53 cores, the AM62L processor provides robust computing with necessary security features such as secure boot. The device enables fast & efficient development with the scalable software development kits (SDK), open-source hardware and design tools. This SoC is designed for smart metering, EV charging, IOT gateways, industrial HMI, patient monitoring among others.

AM62L was developed with a power management architecture that enables lower power dissipation, lower BOM cost and flexible power design. This power architecture requires 4-5 external regulators to supply the main CORE (VDD_CORE), RAM (VDDR_CORE), DDR PHY IO (VDDS_DDR), VDDA analog supply (can be combined with 1.8V IO with proper filtering) and 1.8V/3.3V IO supplies. Table 1-1 highlights some of the benefits of the SoC power architecture.

Note: In the event of any inconsistency between user's guide, application report, or other referenced material, the data sheet specification is the definitive sources.

Table 1-1 AM62L Power Architecture Features

Power Architecture Features	Benefits
✓ Low Power Modes	4 low power modes (RTC Only, RTC + IO + DDR, DeepSleep and Standby) significantly reduce power consumption and allows higher power efficiency and longer battery lifetime.
✓ Active Power	Low active power and OS Idle allows to reduce power during lower activity use cases.
✓ CORE voltage	Differentiated low power capability with 0.75V fixed core voltage supply supports up to 1.25GHz dual A53.
✓ Voltage domain	Single CORE voltage domain enables low cost power design and simpler software control for power management.
✓ Internal dual voltage LDO	Integrates a 3.3V LDO (SDIO) that can be switched to 1.8V to supply SD card interface and support UHS-I speed. This internal LDO allows designers to reduce BOM size and cost by eliminating the need for an external dual voltage LDO.
✓ Power Supply Implementation	Flexible power sequencing and supply consolidation simplifies the PMIC or discrete power implementation and allows optimization for lower BOM size and cost.
✓ Companion PMIC	TPS65214 is a 3.5mm x 3.5mm cost and space optimized power management IC (PMIC) developed to power the AM62L. This is integrated supervisor and sequencer allow to monitor all power rails and fully control the sequencing.