SLVSAR7E June 2011 – October 2016 TPS43350-Q1 , TPS43351-Q1
PRODUCTION DATA.
The TPS43350-Q1 and TPS43351-Q1 include two current-mode synchronous buck controllers designed for the harsh environment in automotive applications. The devices are ideal for use in a multi-rail system with low quiescent requirements, as they automatically operate in low-power mode (consuming typically 30 µA) at light loads. The devices offer protection features such as thermal, soft-start, and overcurrent protection. During short-circuit conditions of the regulator output, activation of the current-foldback feature can limit the current through the MOSFETs for control of power dissipation. The two independent soft-start inputs allow ramp-up of the output voltage independently during start-up.
The programmable range of the switching frequency is from 150 kHz to 600 kHz, as is the frequency of an external clock to which the devices can synchronize. Additionally, the TPS43351-Q1 offers frequency-hopping spread-spectrum operation.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS43350-Q1 | HTSSOP (38) | 12.50 mm × 6.20 mm |
TPS43351-Q1 |
Changes from D Revision (April 2013) to E Revision
Changes from C Revision (September 2012) to D Revision
Changes from B Revision (June 2011) to C Revision
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM) AEC-Q100 Classification Level H2(1) | ±2000 | V | |
Charged-device model (CDM) AEC-Q100 Classification Level C2 | Pins 12, 21, 22, and 27 | ±400 | |||
Pins 1 and 20 | ±750 | ||||
All other pins | ±500 | ||||
Machine model (MM) | Pins 15 and 24 | ±150 | |||
All other pins | ±200 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Buck function: BuckA and BuckB voltage |
Input voltage: , VBAT | 4 | 40 | V |
Enable inputs: ENA, ENB | 0 | 40 | V | |
Boot inputs: CBA, CBB | 4 | 48 | V | |
Phase inputs: PHA, PHB | –0.6 | 40 | V | |
Current-sense voltage: SA1, SA2, SB1, SB2 | 0 | 11 | V | |
Power-good output: PGA, PGB | 0 | 11 | V | |
SYNC, EXTSUP | 0 | 9 | V | |
Temperature | Operating temperature: TA | –40 | 125 | °C |
THERMAL METRIC(1) | TPS43333-Q1 | UNIT | |
---|---|---|---|
DAP (HTSSOP) | |||
38 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 27.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 19.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 15.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.24 | °C/W |
ψJB | Junction-to-board characterization parameter | 6.6 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.2 | °C/W |
NO. | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
1.0 | Input Supply | ||||||
1.1 | VBat | Supply voltage | After initial start-up, condition is satisfied. | 4 | 40 | V | |
1.2 | VIN | Input voltage required for device on initial start-up | 6.5 | 40 | V | ||
Buck regulator operating range after initial start-up | 4 | 40 | V | ||||
1.3 | VIN UV | Buck undervoltage lockout | VIN falling. After a reset, initial start-up conditions may apply.(1) | 3.5 | 3.6 | 3.8 | V |
VIN rising. After a reset, initial start-up conditions may apply.(1) | 3.8 | 4 | V | ||||
1.5 | Iq_LPM_ | LPM quiescent current: TA = 25°C(2) |
VIN = 13 V, BuckA: LPM, BuckB: off | 30 | 40 | µA | |
VIN = 13 V, BuckB: LPM, BuckA: off | 30 | 40 | |||||
VIN = 13 V, BuckA, B: LPM | 35 | 45 | µA | ||||
1.6 | Iq_LPM | LPM quiescent current: TA = 125°C(2) |
VIN = 13 V, BuckA: LPM, BuckB: off | 40 | 50 | µA | |
VIN = 13 V, BuckB: LPM, BuckA: off | 40 | 50 | |||||
VIN = 13 V, BuckA, B: LPM | 45 | 55 | µA | ||||
1.7 | Iq_NRM | Quiescent current: TA = 25°C(2) |
Normal operation, SYNC = High | 4.85 | 5.3 | mA | |
VIN = 13 V, BuckA: CCM, BuckB: off | 7 | 7.6 | mA | ||||
VIN = 13 V, BuckB: CCM, BuckA: off | |||||||
VIN = 13 V, BuckA, B: CCM | |||||||
1.8 | Iq_NRM | Quiescent current: TA = 125°C(2) |
Normal operation, SYNC = High | 5 | 5.5 | mA | |
VIN = 13 V, BuckA: CCM, BuckB: off | 7.5 | 8 | mA | ||||
VIN = 13 V, BuckB: CCM, BuckA: off | |||||||
VIN = 13 V, BuckA, B: CCM | |||||||
1.9 | IBAT_sh | Shutdown current | BuckA, B: off, VBAT = 13 V | 3 | 5 | µA | |
2.0 | Input Voltage - Overvoltage Lockout | ||||||
2.1 | VOVLO | Overvoltage shutdown | VIN rising | 45 | 46 | 47 | V |
VIN falling | 43 | 44 | 45 | V | |||
2.2 | OVLOHys | Hysteresis | 1 | 2 | 3 | V | |
2.3 | OVLOfilter | Filter time | 5 | µs | |||
Gate Driver for PMOS | |||||||
3.1 | rDS(on) | PMOS OFF | 10 | 20 | Ω | ||
3.2 | IPMOS_ON | Gate current | VIN = 13.5 V, VGS = –5 V | 10 | mA | ||
3.3 | tdelay_ON | Turnon delay | C = 10 nF | 5 | 10 | µs | |
4.0 | Buck Controllers | ||||||
4.1 | VBuckA/B | Adjustable output voltage range | 0.9 | 11 | V | ||
4.2 | VREF, NRM | Internal reference voltage and tolerance in normal mode | Measure FBX pin | 0.792 | 0.8 | 0.808 | V |
–1% | 1% | ||||||
4.3 | VREF, LPM | Internal reference voltage and tolerance in low-power mode | Measure FBX pin | 0.784 | 0.8 | 0.816 | V |
–2% | 2% | ||||||
4.4 | VSENSE | V sense for forward current limit in CCM | FBx = 0.75 V (low duty cycles) | 60 | 75 | 90 | mV |
4.5 | V sense for reverse current limit in CCM | FBx = 1 V | –65 | –37.5 | –23 | mV | |
4.6 | VI-Foldback | V sense for output short | FBx = 0 V | 17 | 32.5 | 48 | mV |
4.7 | tdead | Shoot-through delay, blanking time | 100 | ns | |||
4.8 | DCNRM | High-side minimum on-time | 100 | ns | |||
Maximum duty cycle (digitally controlled) | 98.75% | ||||||
4.9 | DCLPM | Duty cycle LPM | 80% | ||||
4.10 | ILPM_Entry | LPM entry threshold load current as fraction of maximum set load current | The exit threshold is specified to be always higher than entry threshold | 1% | . See(3) | ||
ILPM_Exit | LPM exit threshold load current as fraction of maximum set load current | The exit threshold is specified to be always higher than entry threshold | See(3) | 10% | |||
High-Side External NMOS Gate Drivers for Buck Controller | |||||||
4.11 | IGX1_peak | Gate driver peak current | 1.5 | A | |||
4.12 | rDS(on) | Source and sink driver | VREG = 5.8 V, IGX1 current = 200 mA | 2 | Ω | ||
Low-Side NMOS Gate Drivers for Buck Controller | |||||||
4.13 | IGX2_peak | Gate-driver peak current | 1.5 | A | |||
4.14 | rDS(on) | Source and sink driver | VREG = 5.8 V, IGX2 current = 200 mA | 2 | Ω | ||
Error Amplifier (OTA) for Buck Converters | |||||||
4.15 | GmBUCK | Transconductance | COMPA, COMPB = 0.8 V, source/sink = 5 µA, test in feedback loop |
0.72 | 1 | 1.35 | mS |
4.16 | IPULLUP_FBx | Pullup current at FBx pins | FBx = 0 V | 50 | 100 | 200 | nA |
5.0 | Digital Inputs: ENA, ENB, SYNC | ||||||
5.1 | VIH | Higher threshold | VIN = 13 V | 1.7 | V | ||
5.2 | VIL | Lower threshold | VIN = 13 V | 0.7 | V | ||
5.3 | RIH_SYNC | Resistance | VSYNC = 5 V | 500 | kΩ | ||
5.5 | IIL_ENx | Pullup current source on ENA, ENB | VENx = 0 V | 0.5 | 2 | µA | |
6.0 | Switching Parameters – Buck DC-DC Controllers | ||||||
6.1 | fSW_Buck | Buck switching frequency | RT pin: GND | 360 | 400 | 440 | kHz |
6.2 | fSW_Buck | Buck switching frequency | RT pin: 60-kΩ external resistor | 360 | 400 | 440 | kHz |
6.3 | fSW_adj | Buck adjustable range with external resistor | RT pin: external resistor | 150 | 600 | kHz | |
6.4 | fSYNC | Buck synchronization range | External clock input | 150 | 600 | kHz | |
6.5 | fSS | Spread-spectrum spreading | TPS43351-Q1 only | 5% | |||
7.0 | Internal Gate-Driver Supply | ||||||
7.1 | VREG | Internal regulated supply | VIN = 8 V to 18 V, EXTSUP = 0 V, SYNC = High | 5.5 | 5.8 | 6.1 | V |
Load regulation | IVREG = 0 mA to 100 mA, EXTSUP = 0 V, SYNC = High |
0.2% | 1% | ||||
7.2 | VREG(EXTSUP) | Internal regulated supply | EXTSUP = 8.5 V | 7.2 | 7.5 | 7.8 | V |
Load regulation | IEXTSUP = 0 mA to 125 mA, SYNC = High EXTSUP = 8.5 V to 13 V |
0.2% | 1% | ||||
7.3 | VEXTSUP_th | EXTSUP switch-over voltage threshold | IVREG = 0 mA to 100 mA , EXTSUP ramping positive |
4.4 | 4.6 | 4.8 | V |
7.4 | VEXTSUP-Hys | EXTSUP switch-over hysteresis | 150 | 250 | mV | ||
7.5 | IREG-Limit | Current limit on VREG | EXTSUP = 0 V, normal mode as well as LPM | 100 | 400 | mA | |
7.6 | IREG_EXTSUP-Limit | Current limit on VREG when using EXTSUP | IVREG = 0 mA to 100 mA, EXTSUP = 8.5 V, SYNC = High |
125 | 400 | mA | |
8.0 | Soft Start | ||||||
8.1 | ISSx | Soft-start source current | SSA and SSB = 0 V | 0.75 | 1 | 1.25 | µA |
9.0 | Oscillator (RT) | ||||||
9.1 | VRT | Oscillator reference voltage | 1.2 | V | |||
10.0 | Power-Good / Delay | ||||||
10.1 | PGpullup | Pullup for A and B to Sx2 | 50 | kΩ | |||
10.2 | PGth1 | Power-good threshold | FBx falling | –5% | –7% | –9% | |
10.3 | PGhys | Hysteresis | 2% | ||||
10.4 | PGdrop | Voltage drop | IPGA = 5 mA | 450 | mV | ||
10.5 | IPGA = 1 mA | 100 | mV | ||||
10.6 | PGleak | Leakage | VSx2 = VPGx = 13 V | 1 | µA | ||
10.7 | tdeglitch | Power-good deglitch time | 2 | 16 | µs | ||
10.8 | tdelay | Reset delay | External capacitor = 1 nF VBuckX < PGth1 |
1 | ms | ||
10.9 | tdelay_fix | Fixed reset delay | No external capacitor, pin open | 20 | 50 | µs | |
10.10 | IOH | Activate current source (current to charge external capacitor) | 30 | 40 | 50 | µA | |
10.11 | IIL | Activate current sink (current to discharge external capacitor) | 30 | 40 | 50 | µA | |
11.0 | Overtemperature Protection | ||||||
11.1 | Tshutdown | Junction temperature shutdown threshold | 150 | 165 | °C | ||
11.2 | Thys | Junction temperature hysteresis | 15 | °C |
VIN = 12 V | VOUT = 5 V | fSW = 400 kHz |
L = 4.7 µH | RSENSE = 10 mΩ |
VIN = 12 V | VOUT = 5 V | fSW = 400 kHz |
L = 4.7 µH | RSENSE = 10 mΩ |
The TPS43350-Q1 and TPS43351-Q1 devices feature two current-mode synchronous buck controllers. With light loads, the buck controllers can be enabled to automatically operate in low-power mode, consuming just 30 µA of quiescent current. The buck controllers have independent soft-start capability and power-good indicators. Current foldback in the buck controllers provide external MOSFET protection. The switching frequency is programmable over 150 kHz to 600 kHz or can be synchronized to an external clock in the same range. Additionally, the TPS43351-Q1 offers frequency-hopping spread-spectrum operation.
The buck controllers operate using constant-frequency peak-current mode control for optimal transient behavior and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz, depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching frequency to 400 kHz. Using a resistor at RT, one can set another frequency according to Equation 1.
For example:
It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to 600 kHz. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the specified range. The device can also detect a loss of clock at this pin, and on detection of this condition, the device sets the switching frequency to the internal oscillator. The two buck controllers operate at identical switching frequencies, 180 degrees out of phase.
Independent enable inputs from the ENA and ENB pins enable the buck controllers. These are high-voltage pins, with a threshold of 1.7 V for the high level, and with direct connection to the battery permissible for self-bias. The low threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 µA (typical). As a result, an open circuit on these pins enables the respective buck controllers. But with both buck controllers disabled, the device shuts down and consumes a current less than 4 µA.
The right resistor feedback divider network connected to the FBx (feedback) pins sets the output voltage. Choose this network such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100-nA pullup current source as a protection feature in case the pins open up as a result of physical damage.
In order to avoid large inrush currents, the buck controllers have independent programmable soft-start timers. The voltage at the SSx pins acts as the soft-start reference voltage. The 1-µA pullup current available at the SSx pins, in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After start-up, the pullup current ensures that this node is higher than the internal reference of 0.8 V, which then becomes the reference for the buck controllers. Use Equation 2 to calculate the soft-start ramp time..
where
An alternative use of the soft-start pins is as tracking inputs. In this case, connect them to the supply to be tracked via a suitable resistor-divider network.
Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at its set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the output of the error amplifier (COMPx) which serves as a target for the peak inductor current. The device senses the current through the inductor as a differential voltage at Sx1–Sx2 and compares voltage with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing COMPx to fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current matches the load. This process maintains the output voltage in regulation.
The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current reaches its peak value. Once this MOSFET turns off, and after a small delay (shoot-through delay) the lower N-channel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET stays on continuously. In every fourth clock cycle, there is a limit on the duty cycle of 95% in order to charge the bootstrap capacitor at CBx. This allows a maximum duty cycle of 98.75% for the buck regulators. During dropout, the buck regulator switches at one-fourth of its normal frequency.
Clamping of the maximum value of COMPx is such as to limit the maximum current through the inductor to a specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value due to a short-circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus providing current foldback protection. This protects the high-side external MOSFET from excess current (forward-direction current limit).
Similarly, if a fault condition shorts the output to a high voltage and the low-side MOSFET turns fully on, the COMPx node drops low. A clamp is on its lower end as well, in order to limit the maximum current in the low-side MOSFET (reverse-direction current limit).
An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This specified value is for low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5-V output and 12-V input), 50 mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics provide a guide for using the correct current-limit sense voltage.
The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range. This allows DCR current sensing using the dc resistance of the inductor for higher efficiency. Figure 11 shows DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency, it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance. Hence, it may often be advantageous to use the more-accurate sense resistor for current sensing.
Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable operation at all conditions. For optimal performance of this circuit, choose the inductor and sense resistor according to Equation 3.
where
Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-drain output at the PGx pins. An internal 50-kΩ pullup resistor to Sx2 is available, or use of an external resistor is possible. Shutdown of a buck controller causes an internal pulldown of the power-good indicator. Connecting the pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow through the resistor when the buck controller is in the powered-down state.
In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to its set value after a long negative transient, assertion of the power-good indicator (release of the open-drain pin) occurs after the same delay. Use of this delay can pauses the delay of the reset. Program the duration of the delay of by using a suitable capacitor at the DLYAB pin according to Equation 4.
When the DLYAB pin is open, the delay setting is for a default value of 20 µs typical. The power-good delay timing is common to both the buck rails, but the power-good comparators and indicators function independently.
An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. An open or low on the SYNC pin allows the buck controllers to operate in discontinuous mode at light loads by turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.
In discontinuous mode, as the load decreases, the duration when both the high-side and low-side MOSFETs turn off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8 V, the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1% of the set full-load current if the inductor and the sense resistor have been chosen appropriately as recommended in the Slope Compensation section.
In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference. Whenever the FBx value falls below the reference, the high-side MOSFET turns on for a pulse duration inversely proportional to the difference – Sx2. At the end of this on-time, the high-side MOSFET turns off and the current in the inductor decays until it becomes zero. The low-side MOSFET does not turn on. The next pulse occurs the next time FBx falls below the reference value. This results in a constant volt-second ton hysteretic operation with a total device quiescent current consumption of 30 µA when a single buck channel is active and 35 µA when both channels are active.
As the load increases, the pulses become more and more frequent and move closer to each other until the current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher than 80% duty cycle of the high-side MOSFET.
The TPS43350-Q1 and TPS43351-Q1 can support the full current load during low-power mode until the transition to normal mode takes place. The design ensures that exit of the low-power mode occurs at 10% (typical) of full-load current if the selection of inductor and sense resistor is as recommended. Moreover, there is always a hysteresis between the entry and exit thresholds to avoid oscillating between the two modes.
In the event that both buck controllers are active, low-power mode is only possible when both buck controllers have light loads that are low enough for low-power-mode entry.
The TPS43351-Q1 features a frequency-hopping pseudo-random spectrum spreading architecture. On this device, whenever the SYNC pin is high, the internal oscillator frequency varies from one cycle to the next within a band of ±5% around the value programmed by the resistor at the RT pin. The implementation uses a linear feedback shift register that changes the frequency of the internal oscillator based on a digital code. The shift register is long enough to make the hops pseudo-random in nature and is designed in such a way that the frequency shifts only by one step at each cycle to avoid large jumps in the buck switching frequencies.
SYNC TERMINAL |
FREQUENCY SPREAD SPECTRUM (FSS) | COMMENTS |
---|---|---|
External clock | Not active | Device in forced continuous mode, internal PLL locks into external clock between 150 kHz and 600 kHz. |
Low or open | Not active | Device can enter discontinuous mode. Automatic LPM entry and exit, depending on load conditions |
High | TPS43350-Q1: FSS not active | Device in forced continuous mode |
TPS43351-Q1: FSS active |
The gate-driver supplies of the buck and boost controllers are from an internal linear regulator whose output (5.8 V typical) is on the VREG pin and requires decoupling with a ceramic capacitor in the range of 3.3 µF to 10 µF. This pin has internal current-limit protection; do not use it to power any other circuits.
VIN powers the VREG linear regulator by default when the EXTSUP voltage is lower than 4.6 V (typical). In case VIN expected to go to high levels, there can be excessive power dissipation in this regulator, especially at high switching frequencies and when using large external MOSFETs. In this case, it is advantageous to power this regulator from the EXTSUP pin, which can be connected to a supply lower than VIN but high enough to provide the gate drive. When the voltage on EXTSUP is greater than 4.6 V, the linear regulator automatically switches to EXTSUP as its input, to provide this advantage. Efficiency improvements are possible when using one of the switching regulator rails from the TPS4335x-Q1 or any other voltage available in the system to power EXTSUP. The maximum voltage for application to EXTSUP is 9 V.
Using a voltage above 5.8 V (sourced by VIN) for EXTSUP is advantageous, as it provides a large gate drive and hence better on-resistance of the external MOSFETs. When using EXTSUP, always keep the buck rail supplying EXTSUP enabled. Alternatively, if it is necessary to switch off the buck rail supplying EXTSUP, place a diode between the buck rail and EXTSUP. During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt regulator powered from VIN and has a typical value of 7.5 V. Current-limit protection for VREG is available in low-power mode as well. If EXTSUP is unused, leave the pin open without a capacitor installed.
The TPS4335x-Q1 includes a gate driver for an external P-channel MOSFET which can be connected across the reverse-battery diode. This is useful to reduce power losses and the voltage drop over a typical diode. The gate driver provides a swing of 6 V typical below the VIN voltage in order to drive a P-channel MOSFET.
The TPS4335x-Q1 starts up at a VIN voltage of 6.5 V (minimum), required for the internal supply (VREG). Once it has started up, the device operates down to a VIN voltage of 3.6 V; below this voltage level, the undervoltage lockout disables the device. Note: if VIN drops, VREG drops as well; hence, the gate-drive voltage decreases, whereas the digital logic is fully functional. A voltage of 46 V at VIN triggers the overvoltage comparator, which shuts down the device. In order to prevent transient spikes from shutting down the device, under- and overvoltage protection have filter times of 5 µs (typical).
When the voltages return to the normal operating region, the enabled switching regulators startwith a new soft-start ramp for the buck regulators.
The TPS4335x-Q1 protects itself from overheating using an internal thermal shutdown circuit. If the die temperature exceeds the thermal shutdown threshold of 165ºC due to excessive power dissipation (for example, due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers turn off. Then restart when the temperature has fallen by 15ºC.
Table 2 lists the modes of operation for the device.
ENABLE AND INHIBIT PINS | BUCK CONTROLLER STATUS | DEVICE STATUS | QUIESCENT CURRENT | ||
---|---|---|---|---|---|
ENA | ENB | SYNC | |||
Low | Low | X | Shutdown | Shutdown | Approximately 4 µA |
Low | High | Low | BuckB running | BuckB: LPM enabled | Approximately 30 µA (light loads) |
High | BuckB: LPM inhibited | mA range | |||
High | Low | Low | BuckA running | BuckA: LPM enabled | Approximately 30 µA (light loads) |
High | BuckA: LPM inhibited | mA range | |||
High | High | Low | BuckA and BuckB running | BuckA and BuckB: LPM enabled | Approximately 35 µA (light loads) |
High | BuckA and BuckB: LPM inhibited | mA range |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS4335x-Q1 devices are dual synchronous buck controllers used to convert a higher-input voltage to two lower-output voltages. The following sections have the component values and calculations that are a good starting point for use in the application. Some of the values in the equations are theoretical values, to improve the performance of the device may require further optimization of these values.
Table 3 lists the design-goal parameters.
The following example illustrates the design process and component selection for the TPS43350-Q1.
This is a starting point, and theoretical representation of the values to be used for the application; improving the performance of the device may require further optimization of the derived components.
NAME | COMPONENT PROPOSAL | VALUE |
---|---|---|
L1 | MSS1278T-822ML (Coilcraft) | 8.2 µH |
L2 | MSS1278T-153ML (Coilcraft) | 15 µH |
D1 | SK103 (Micro Commercial Components) | |
SWRB | IRF7416 (International Rectifier) | |
SWAH, SWAL, SWBH, SWBL | Si4840DY-T1-E3 (Vishay) | |
COUTA, COUTB | ECASD91A107M010K00 (Murata) | 100 µF |
CIN | EEEFK1V331P (Panasonic) | 330 µF |
This is higher than the minimum on-time specified (100 ns typical). Hence, the minimum duty cycle is achievable at this frequency.
Based on the typical characteristics for VSENSE limit with VIN versus duty cycle, the sense limit is approximately 65 mV (at VIN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple currents, choose VSENSE with a maximum of 50 mV.
Select 15 mΩ.
As explained in the description of the buck controllers, for optimal slope compensation and loop response, the inductor should be chosen such that:
KFLR = Coil selection constant = 200
Choose a standard value of 8.2 µH. For the buck converter, the inductor saturation currents and core should be chosen to sustain the maximum currents.
At nominal input voltage of 12 V, this inductor value causes a ripple current of 30% of IO max ≈ 1 A.
Select an output capacitance COUTA of 100 µF with low ESR in the range of 10 mΩ. This gives ∆VO(Ripple) ≈ 15 mV and ∆V drop of ≈ 180 mV during a load step, which does not trigger the power-good comparator and is within the required limits.
Use the following guidelines to set frequency poles, zeroes and crossover values for a tradeoff between stability and transient response.
Use the standard value of R3 = 24 kΩ,
Where VOUT = 5 V, COUTx = 100 µF, GmBUCK = 1 mS, VREF = 0.8 V
KCFB = 0.125 / RSENSE = 8.33 S (0.125 is an internal constant)
Use the standard value of 1.5 nF.
The resulting bandwidth of buck converter, fC:
This is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1:
This is close to the fC / 10 guideline of 5 kHz.
The second pole frequency fP2:
This is close to the fSW / 2 guideline of 200 kHz. Hence, the design satisfies all requirements for a good loop.
Choose the divider current through R1 and R2 to be 50 µA. Then
and
Therefore, R2 = 16 kΩ and R1 = 84 kΩ.
Using the same method as for VBuckA produces the following parameters and components.
This is higher than the minimum duty cycle specified (100 ns typical).
∆Iripple current ≈ 0.4 A (approximately 20% of IOUT max)
Select an output capacitance CO of 100 µF with low ESR in the range of 10 mΩ. Assume fC = 50 kHz.
Use the standard value of R3 = 30 kΩ.
This is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1:
This is close to the fC guideline of 5 kHz.
The second pole frequency fP2:
This is close to the fSW / 2 guideline of 200 kHz.
Hence, the design satisfies all requirements for a good loop.
Choose the divider current through R1 and R2 to be 50 µA. Then
and
Therefore, R2 = 16 kΩ and R1 = 50 kΩ.
An internal supply, which is 5.8 V typical under normal operating conditions, provides the gate-drive supply for these MOSFETs. The output is a totem pole allowing full voltage drive of VREG to the gate with peak output current of 1.5 A. The reference for the high-side MOSFET is a floating node at the phase terminal (PHx), and the reference for the low-side MOSFET is the power-ground (PGx) terminal. For a particular application, select these MOSFETs with consideration for the following parameters: rDS(on), gate charge Qg, drain-to-source breakdown voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.
The times tr and tf denote the rising and falling times of the switching node and have a relationship to the gate-driver strength of the TPS43350x-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the conduction losses, which are minimal when the on-resistance of the MOSFET is low. The second term denotes the transition losses, which arise due to the full application of the input voltage across the drain-source of the MOSFET as it turns on or off. They are lower at low currents and when the switching time is low.
In addition, during dead time td when both the MOSFETs are off, the body diode of the low-side MOSFET conducts, increasing the losses. The second term in the foregoing equation denotes this. Using external Schottky diodes in parallel to the low-side MOSFETs of the buck converters helps to reduce this loss.
NOTE
The rDS(on) has a positive temperature coefficient, and TC term for rDS(on) accounts for that fact. TC = d × delta T[°C]. The temperature coefficient d is available as a normalized value from MOSFET data sheets and can be assumed to be 0.005 / °C as a starting value.
VIN = 12 V | VOUT = 5 V | fSW = 400 kHz |
L = 4.7 µH | RSENSE = 10 mΩ |
VIN = 12 V | VOUT = 5 V | fSW = 400 kHz | ||
LÄ = 4.7 µH | RSENSE = 10 mΩ |
VIN = 12 V | VOUT = 5 V | fSW = 400 kHz |
L = 4.7 µH | RSENSE = 10 mΩ |