The TPS54227 device is an adaptive ON-time D-CAP2 mode synchronous buck converter. The TPS54227 enables system designers to complete the bus regulators for a suite of various end equipment with a cost-effective, low component count, low standby current solution. The main control loop for the TPS54227 uses the D-CAP2 mode control which provides a fast transient response with no external compensation components. The TPS54227 also has a proprietary circuit that enables the device to adopt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VIN input. The output voltage can be programmed between 0.76 V and 7 V. The device also features an adjustable soft-start time. The TPS54227 is available in the 8-pin HSOP package and 10-pin VSON, and is designed to operate from –40°C to 85°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS54227 | SO PowerPAD (8) | 4.89 mm × 3.90 mm |
VSON (10) | 3.00 mm × 3.00 mm |
Changes from B Revision (June 2013) to C Revision
Changes from A Revision (October 2011) to B Revision
Changes from * Revision (May 2010) to A Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | DDA | DRC | ||
EN | 1 | 1 | I | Enable input control. EN is active high and must be pulled up to enable the device. |
Exposed Thermal Pad | — | G | Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to GND. | |
— | Thermal pad of the package. PGND power ground return of internal low-side FET. Must be soldered to achieve appropriate dissipation. | |||
GND | 5 | 5 | G | Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at a single point. |
SS | 4 | 4 | O | Soft-start control. An external capacitor should be connected to GND. |
SW | 6 | 6, 7 | O | Switch node connection between high-side NFET and low-side NFET. |
VBST | 7 | 8 | I | Supply input for the high-side FET gate drive circuit. Connect 0.1-µF capacitor between VBST and SW pins. An internal diode is connected between VREG5 and VBST. |
VFB | 2 | 2 | I | Converter feedback input. Connect to output voltage with feedback resistor divider. |
VIN | 8 | 9, 10 | P | Input voltage supply pin. |
VREG5 | 3 | 3 | O | 5.5-V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active when EN is low. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VIN, EN | –0.3 | 20 | V |
VBST | –0.3 | 26 | V | |
VBST (10-ns transient) | –0.3 | 28 | V | |
VBST (vs SW) | –0.3 | 6.5 | V | |
VFB, SS | –0.3 | 6.5 | V | |
SW | –2 | 20 | V | |
SW (10-ns transient) | –3 | 22 | V | |
Output voltage | VREG5 | –0.3 | 6.5 | V |
GND | –0.3 | 0.3 | V | |
Voltage from GND to thermal pad, Vdiff | –0.2 | 0.2 | V | |
Operating junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
THERMAL METRIC(1) | TPS54227 | UNIT | ||
---|---|---|---|---|
DDA (HSOP) | DRC (VSON) | |||
8 PINS | 10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 45.3 | 43.9 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 54.8 | 55.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 16.2 | 18.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 6.6 | 0.7 | °C/W |
ψJB | Junction-to-board characterization parameter | 16 | 19.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 8.5 | 5.3 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY CURRENT | ||||||
IVIN | Operating - non-switching supply current | VIN current, TA = 25°C, EN = 5 V, VFB = 0.8 V | 800 | 1200 | μA | |
IVINSDN | Shutdown supply current | VIN current, TA = 25°C, EN = 0 V | 5 | 10 | μA | |
LOGIC THRESHOLD | ||||||
VENH | EN high-level input voltage | EN | 1.6 | V | ||
VENL | EN low-level input voltage | EN | 0.6 | V | ||
REN | EN pin resistance to GND | VEN = 12 V | 220 | 440 | 880 | kΩ |
VFB VOLTAGE AND DISCHARGE RESISTANCE | ||||||
VFBTH | VFB threshold voltage | TA = 25°C, VO = 1.05 V, continuous mode | 749 | 765 | 781 | mV |
IVFB | VFB input current | VFB = 0.8 V, TA = 25°C | 0 | ±0.1 | μA | |
VREG5 OUTPUT | ||||||
VVREG5 | VREG5 output voltage | TA = 25°C, 6 V < VIN < 18 V, 0 < IVREG5 < 5 mA | 5.2 | 5.5 | 5.7 | V |
VLN5 | Line regulation | 6 V < VIN < 18 V, IVREG5 = 5 mA | 25 | mV | ||
VLD5 | Load regulation | 0 mA < IVREG5 < 5 mA | 100 | mV | ||
IVREG5 | Output current | VIN = 6 V, VREG5 = 4 V, TA = 25°C | 60 | mA | ||
MOSFET | ||||||
RDS(on)h | High-side switch resistance (DDA) | 25°C, VBST - SW = 5.5 V | 155 | mΩ | ||
High-side switch resistance (DRC) | 165 | |||||
RDS(on)l | Low-side switch resistance | 25°C | 108 | mΩ | ||
CURRENT LIMIT | ||||||
Iocl | Current limit | L out = 2.2 μH(1) | 2.5 | 3.3 | 4.7 | A |
THERMAL SHUTDOWN | ||||||
TSDN | Thermal shutdown threshold | Shutdown temperature (1) | 165 | °C | ||
Hysteresis (1) | 35 | |||||
ON-TIME TIMER CONTROL | ||||||
tON | ON-time | VIN = 12 V, VO = 1.05 V | 150 | ns | ||
tOFF(MIN) | Minimum OFF-time | TA = 25°C, VFB = 0.7 V | 260 | 310 | ns | |
SOFT-START | ||||||
ISSC | SS charge current | VSS = 1V | 1.4 | 2 | 2.6 | μA |
ISSD | SS discharge current | VSS = 0.5 V | 0.1 | 0.2 | mA | |
UVLO | ||||||
UVLO | UVLO threshold | Wake up VREG5 voltage | 3.45 | 3.75 | 4.05 | V |
Hysteresis VREG5 voltage | 0.13 | 0.32 | 0.48 |