The DRV8836 provides an integrated motor driver solution for cameras, consumer products, toys, and other low-voltage or battery-powered motion control applications. The device has two H-bridge drivers, and can drive two DC motors or one stepper motor, as well as other devices like solenoids. The output driver block for each consists of N-channel power MOSFET configured as an H-bridge to drive the motor winding. An internal charge pump generates gate drive voltages.
The DRV8836 supplies up to 1.5-A of output current per H-bridge. It operates on a power supply voltage from 2 V to 7 V.
PHASE/ENABLE and IN/IN interfaces can be selected which are compatible with industry-standard devices. A low-power sleep mode is provided which turns off all unnecessary logic to provide a very low current state.
Internal shutdown functions are provided for overcurrent protection, short-circuit protection, undervoltage lockout, and overtemperature.
The DRV8836 is packaged in a tiny 12-pin WSON package (Eco-friendly: RoHS and no Sb/Br).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DRV8836 | WSON (12) | 2.00 mm x 3.00 mm |
Changes from C Revision (December 2015) to D Revision
Changes from B Revision (January 2014) to C Revision
Changes from A Revision (September 2013) to B Revision
PIN | I/O(1) | DESCRIPTION | EXTERNAL COMPONENTS OR CONNECTIONS |
|
---|---|---|---|---|
NAME | NO. | |||
POWER AND GROUND | ||||
GND, Thermal pad | 6 | — | Device ground | |
VCC | 1 | — | Device and motor supply | Bypass to GND with a 0.1-μF (minimum) ceramic capacitor |
CONTROL | ||||
AIN1/APHASE | 10 | I | Bridge A input 1/PHASE input | IN/IN mode: Logic high sets AOUT1 high PH/EN mode: Sets direction of H-bridge A Internal pulldown resistor |
AIN2/AENBL | 9 | I | Bridge A input 2/ENABLE input | IN/IN mode: Logic high sets AOUT2 high PH/EN mode: Logic high enables H-bridge A Internal pulldown resistor |
BIN1/BPHASE | 8 | I | Bridge B input 1/PHASE input | IN/IN mode: Logic high sets BOUT1 high PH/EN mode: Sets direction of H-bridge B Internal pulldown resistor |
BIN2/BENBL | 7 | I | Bridge B input 2/ENABLE input | IN/IN mode: Logic high sets BOUT2 high PH/EN mode: Logic high enables H-bridge B Internal pulldown resistor |
MODE | 11 | I | Input mode select | Logic low selects IN/IN mode Logic high selects PH/EN mode Internal pulldown resistor |
nSLEEP | 12 | I | Sleep input | Active low places part in low-power sleep state Internal pulldown resistor |
OUTPUT | ||||
AOUT1 | 2 | O | Bridge A output 1 | Connect to motor winding A |
AOUT2 | 3 | O | Bridge A output 2 | |
BOUT1 | 4 | O | Bridge B output 1 | Connect to motor winding B |
BOUT2 | 5 | O | Bridge B output 2 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Power supply voltage, VCC | –0.3 | 7 | V | ||
Digital input pin voltage | –0.5 | VCC + 0.5 | V | ||
Peak motor drive output current | Internally limited | A | |||
Continuous motor drive output current per H-bridge(3) | –1.5 | 1.5 | A | ||
TJ | Operating junction temperature | –40 | 150 | °C | |
Tstg | Storage temperature | –60 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC | Device power supply voltage | 2 | 7 | V |
VIN | Logic level input voltage | 0 | VCC | V |
IOUT | H-bridge output current(1) | 0 | 1.5 | A |
fPWM | Externally applied PWM frequency | 0 | 250 | kHz |
THERMAL METRIC(1) | DRV8836 | UNIT | |
---|---|---|---|
DSS (WSON) | |||
12 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 50.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 58 | °C/W |
RθJB | Junction-to-board thermal resistance | 19.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 20 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 6.9 | °C/W |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
1 | t1 | Delay time, xPHASE high to xOUT1 low | 210 | ns | |
2 | t2 | Delay time, xPHASE high to xOUT2 high | 150 | ns | |
3 | t3 | Delay time, xPHASE low to xOUT1 high | 150 | ns | |
4 | t4 | Delay time, xPHASE low to xOUT2 low | 210 | ns | |
5 | t5 | Delay time, xENBL high to xOUTx high | 150 | ns | |
6 | t6 | Delay time, xENBL high to xOUTx low | 150 | ns | |
7 | t7 | Output enable time | 210 | ns | |
8 | t8 | Output disable time | 210 | ns | |
9 | t9 | Delay time, xINx high to xOUTx high | 125 | ns | |
10 | t10 | Delay time, xINx low to xOUTx low | 125 | ns | |
11 | tR | Output rise time | 20 | 188 | ns |
12 | tF | Output fall time | 8 | 30 | ns |