TPD8S300 USB Type-C Port Protector: Short-to-VBUS Overvoltage and IEC ESD Protection

1 Features

4-Channels of Short-to-V_BUS Overvoltage Protection (CC1, CC2, SBU1, SBU2): 24-V_DC Tolerant
8-Channels of IEC 61000-4-2 ESD Protection (CC1, CC2, SBU1, SBU2, DP_T, DM_T, DP_B, DM_B)
CC1, CC2 Overvoltage Protection FETs 600 mA capable for passing V_CONN power
CC Dead Battery Resistors integrated for handling dead battery use case in mobile devices
3-mm × 3-mm WQFN Package

2 Applications

Laptop PC
Tablets
Smartphones
Monitors and TVs
Docking Stations

3 Description

The TPD8S300 is a single chip USB Type-C port protection solution that provides 20-V Short-to-V_BUS overvoltage and IEC ESD protection.

Since the release of the USB Type-C connector, many products and accessories for USB Type-C have been released which do not meet the USB Type-C specification. One example of this is USB Type-C Power Delivery adaptors that only place 20 V on the V_BUS line. Another concern for USB Type-C is that mechanical twisting and sliding of the connector could short pins due to the close proximity they have in this small connector. This can cause 20-V V_BUS to be shorted to the CC and SBU pins. Also, due to the close proximity of the pins in the Type-C connector, there is a heightened concern that debris and moisture will cause the 20-V V_BUS pin to be shorted to the CC and SBU pins.

These non-ideal equipments and mechanical events make it necessary for the CC and SBU pins to be 20-V tolerant, even though they only operate at 5 V or lower. The TPD8S300 enables the CC and SBU pins to be 20-V tolerant without interfering with normal operation by providing overvoltage protection on the CC and SBU pins. The device places high voltage FETs in series on the SBU and CC lines. When a voltage above the OVP threshold is detected on these lines, the high voltage switches are opened up, isolating the rest of the system from the high voltage condition present on the connector.

Finally, most systems require IEC 61000-4-2 system level ESD protection for their external pins. The TPD8S300 integrates IEC 61000-4-2 ESD protection for the CC1, CC2, SBU1, SBU2, DP_T (Top side D+), DM_T (Top Side D–), DP_B (Bottom Side D+), DM_B (Bottom Side D–) pins, removing the need to place high voltage TVS diodes externally on the connector.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPD8S300	WQFN (20)	3.00 mm × 3.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Application Diagram

4 Revision History

Changes from A Revision (September 2016) to B Revision

First public release of the data sheetGo

5 Device Comparison Table

Part Number	Over Voltage Protected Channels	IEC 61000-4-2 ESD Protected Channels
TPD6S300	4-Ch (CC1, CC2, SBU1, SBU2)	6-Ch (CC1, CC2, SBU1, SBU2, DP, DM)
TPD8S300	4-Ch (CC1, CC2, SBU1, SBU2)	8-Ch (CC1, CC2, SBU1, SBU2, DP_T, DM_T, DP_B, DM_B)

6 Pin Configuration and Functions

RUK Package

20 Pin WQFN

Top View

Pin Functions

PIN		TYPE	DESCRIPTION
NO.	NAME	TYPE	DESCRIPTION
1	C_SBU1	I/O	Connector side of the SBU1 OVP FET. Connect to either SBU pin of the USB Type-C connector
2	C_SBU2	I/O	Connector side of the SBU2 OVP FET. Connect to either SBU pin of the USB Type-C connector
3	VBIAS	Power	Pin for ESD support capacitor. Place a 0.1-µF capacitor on this pin to ground
4	C_CC1	I/O	Connector side of the CC1 OVP FET. Connect to either CC pin of the USB Type-C connector
5	C_CC2	I/O	Connector side of the CC2 OVP FET. Connect to either CC pin of the USB Type-C connector
6	RPD_G2	I/O	Short to C_CC2 if dead battery resistors are needed. If dead battery resistors are not needed, short pin to GND
7	RPD_G1	I/O	Short to C_CC1 if dead battery resistors are needed. If dead battery resistors are not needed, short pin to GND
8	GND	GND	Ground
9	FLT	O	Open drain for fault reporting
10	V_PWR	Power	2.7-V-3.6-V power supply
11	CC2	I/O	System side of the CC2 OVP FET. Connect to either CC pin of the CC/PD controller
12	CC1	I/O	System side of the CC1 OVP FET. Connect to either CC pin of the CC/PD controller
13	GND	GND	Ground
14	SBU2	I/O	System side of the SBU2 OVP FET. Connect to either SBU pin of the SBU MUX
15	SBU1	I/O	System side of the SBU1 OVP FET. Connect to either SBU pin of the SBU MUX
16	D4	I/O	USB2.0 IEC ESD protection. Connect to any of the USB2.0 pins of the USB Type-C connector
17	D3	I/O	USB2.0 IEC ESD protection. Connect to any of the USB2.0 pins of the USB Type-C connector
18	GND	GND	Ground
19	D2	I/O	USB2.0 IEC ESD protection. Connect to any of the USB2.0 pins of the USB Type-C connector
20	D1	I/O	USB2.0 IEC ESD protection. Connect to any of the USB2.0 pins of the USB Type-C connector
—	Thermal Pad	GND	Internally connected to GND. Used as a heatsink. Connect to the PCB GND plane

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_I	Input voltage	V_PWR	–0.3	4	V
V_I	Input voltage	RPD_G1, RPD_G2	–0.3	24	V
V_O	Output voltage	FLT	–0.3	6	V
V_O	Output voltage	VBIAS	–0.3	24	V
V_IO	I/O voltage	D1, D2, D3, D4	–0.3	6	V
		CC1, CC2, SBU1, SBU2	–0.3	6	V
		C_CC1, C_CC2, C_SBU1, C_SBU2	–0.3	24	V
T_A	Operating free air temperature		–40	85	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings—JEDEC Specification

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾		±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾		±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance.

7.3 ESD Ratings—IEC Specification

				VALUE	UNIT
V_(ESD)	Electrostatic discharge⁽¹⁾	IEC 61000-4-2, C_CC1, C_CC2, D1, D2, D3, D4	Contact discharge	±8000	V
		IEC 61000-4-2, C_CC1, C_CC2, D1, D2, D3, D4	Air-gap discharge	±15000
		IEC 61000-4-2, C_SBU1, C_SBU2	Contact discharge	±6000
		IEC 61000-4-2, C_SBU1, C_SBU2	Air-gap discharge	±15000

(1) Tested on the TPD8S300 EVM connected to the TPS65982 EVM.

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
V_I	Input voltage	V_PWR	2.7	3.3	3.6	V
V_I	Input voltage	RPD_G1, RPD_G2	0		5.5	V
V_O	Output voltage	FLT pull-up resistor power rail	2.7		5.5	V
V_IO	I/O voltage	D1, D2, D3, D4	–0.3		5.5	V
		CC1, CC2, C_CC1, C_CC2	0		5.5	V
		SBU1, SBU2, C_SBU1, C_SBU2	0		4.3	V
I_VCONN	V_CONN current	Current flowing into CC1/2 and flowing out of C_CC1/2, VCCx – VC_CCx ≤ 250 mV			600	mA
I_VCONN	V_CONN current	Current flowing into CC1/2 and flowing out of C_CC1/2, T_J ≤ 105°C			1.25	A
	External components⁽¹⁾	FLT pull-up resistance	1.7		300	kΩ
		VBIAS capacitance⁽²⁾		0.1		µF
		V_PWR capacitance	0.3	1		µF

(1) For recommended values for capacitors and resistors, the typical values assume a component placed on the board near the pin. Minimum and maximum values listed are inclusive of manufacturing tolerances, voltage derating, board capacitance, and temperature variation. The effective value presented must be within the minimum and maximums listed in the table.

(2) The VBIAS pin requires a minimum 35-V_DC rated capacitor. A 50-V_DC rated capacitor is recommended to reduce capacitance derating. See the VBIAS Capacitor Selection section for more information on selecting the VBIAS capacitor.

7.5 Thermal Information

THERMAL METRIC⁽¹⁾		TPD8S300	UNIT
		RUK (WQFN)
		20 PINS
R_θJA	Junction-to-ambient thermal resistance	45.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	48.8	°C/W
R_θJB	Junction-to-board thermal resistance	17.1	°C/W
ψ_JT	Junction-to-top characterization parameter	0.6	°C/W
ψ_JB	Junction-to-board characterization parameter	17.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
CC OVP Switches
R_ON	On resistance of CC OVP FETs, T_J ≤ 85°C	CCx = 5.5 V		278	392	mΩ
R_ON	On resistance of CC OVP FETs, T_J ≤ 105°C	CCx = 5.5 V		278	415	mΩ
R_ONFLAT	On resistance flatness	Sweep CCx voltage between 0 V and 1.2 V			5	mΩ
C_{ON_CC}	Equivalent on capacitance	Capacitance from C_CCx or CCx to GND when device is powered. VC_CCx/VCCx = 0 V to 1.2 V , f = 400 kHz	60	74	120	pF
RD_DB	Dead battery pull-down resistance (only present when device is unpowered). Effective resistance of R_D and FET in series	V_C_CCx = 2.6 V	4.1	5.1	6.1	kΩ
VTH_DB	Threshold voltage of the pulldown FET in series with RD during dead battery	I_CC = 80 µA	0.5	0.9	1.2	V
V_OVPCC	OVP threshold on CC pins	Place 5.5 V on C_CCx. Step up C_CCx until the FLT pin is asserted	5.75	6	6.2	V
V_{OVPCC_HYS}	Hysteresis on CC OVP	Place 6.5 V on C_CCx. Step down the voltage on C_CCx until the FLT pin is deasserted. Measure difference between rising and falling OVP threshold for CC		50		mV
BW_ON	On bandwidth single ended (–3 dB)	Measure the –3-dB bandwidth from C_CCx to CCx. Single ended measurement, 50-Ω system. Vcm = 0.1 V to 1.2 V		100		MHz
V_{STBUS_CC}	Short-to-VBUS tolerance on the CC pins	Hot-Plug C_CCx with a 1 meter USB Type C Cable, place a 30-Ω load on CCx			24	V
V_{STBUS_CC_CLAMP}	Short-to-VBUS system-side clamping voltage on the CC pins (CCx)	Hot-Plug C_CCx with a 1 meter USB Type C Cable. Hot-Plug voltage C_CCx = 24 V. VPWR = 3.3 V. Place a 30-Ω load on CCx		8		V
SBU OVP Switches
R_ON	On resistance of SBU OVP FETs	SBUx = 3.6 V. –40°C ≤ T_J ≤ +85°C		4	6.5	Ω
R_ONFLAT	On resistance flatness	Sweep SBUx voltage between 0 V and 3.6 V. –40°C ≤ T_J ≤ +85°C		0.7	1.5	Ω
C_{ON_SBU}	Equivalent on capacitance	Capacitance from SBUx or C_SBUx to GND when device is powered. Measure at VC_SBUx/VSBUx = 0.3 V to 3.6 V		6		pF
V_OVPSBU	OVP threshold on SBU pins	Place 3.6 V on C_SBUx. Step up C_SBUx until the FLT pin is asserted	4.35	4.5	4.7	V
V_{OVPSBU_HYS}	Hysteresis on SBU OVP	Place 5 V on C_CCx. Step down the voltage on C_CCx until the FLT pin is deasserted. Measure difference between rising and falling OVP threshold for C_SBUx		50		mV
BW_ON	On bandwidth single ended (–3 dB)	Measure the –3-dB bandwidth from C_SBUx to SBUx. Single ended measurement, 50-Ω system. Vcm = 0.1 V to 3.6 V		1000		MHz
X_TALK	Crosstalk	Measure crosstalk at f = 1 MHz from SBU1 to C_SBU2 or SBU2 to C_SBU1. Vcm1 = 3.6 V, Vcm2 = 0.3 V. Be sure to terminate open sides to 50 Ω		–80		dB
V_{STBUS_SBU}	Short-to-VBUS tolerance on the SBU pins	Hot-Plug C_SBUx with a 1 meter USB Type C Cable. Put a 150-nF capacitor in series with a 40-Ω resistor to GND on SBUx			24	V
V_{STBUS_SBU_CLAMP}	Short-to-VBUS system-side clamping voltage on the SBU pins (SBUx)	Hot-Plug C_SBUx with a 1 meter USB Type C Cable. Hot-Plug voltage C_SBUx = 24 V. VPWR = 3.3 V. Put a 100-nF capacitor in series with a 40-Ω resistor to GND on SBUx		8		V
Power Supply and Leakage Currents
V_{PWR_UVLO}	V_PWR under voltage lockout	Place 1 V on VPWR and raise voltage until SBU or CC FETs turnon	2.1	2.3	2.5	V
V_{PWR_UVLO_HYS}	V_PWR UVLO hysteresis	Place 3 V on VPWR and lower voltage until SBU or CC FETs turnoff; measure difference between rising and falling UVLO to calculate hysteresis	100	150	200	mV
I_VPWR	V_PWR supply current	VPWR = 3.3 V (typical), VPWR = 3.6 V (maximum). –40°C ≤ T_J ≤ +85°C.		90	120	µA
I_{CC_LEAK}	Leakage current for CC pins when device is powered	VPWR = 3.3 V, VC_CCx = 3.6 V, CCx pins are floating, measure leakage into C_CCx pins. Result must be same if CCx side is biased and C_CCx is left floating.			5	µA
I_{SBU_LEAK}	Leakage current for SBU pins when device is powered	VPWR = 3.3 V, VC_SBUx = 3.6 V, SBUx pins are floating, measure leakge into C_SBUx pins. Result must be same if SBUx side is biased and C_SBUx is left floating. –40°C ≤ T_J ≤ 85°C.			3	µA
I_{C_CC_LEAK_OVP}	Leakage current for CC pins when device is in OVP	VPWR = 0 V or 3.3 V, VC_CCx = 24 V, CCx pins are set to 0 V, measure leakage into C_CCx pins			1200	µA
I_{C_SBU_LEAK_OVP}	Leakage current for SBU pins when device is in OVP	VPWR = 0 V or 3.3 V, VC_SBUx = 24 V, SBUx pins are set to 0 V, measure leakage into C_SBUx pins			400	µA
I_{CC_LEAK_OVP}	Leakage current for CC pins when device is in OVP	VPWR = 0 V or 3.3 V, VC_CCx = 24 V, CCx pins are set to 0 V, measure leakage out of CCx pins			30	µA
I_{SBU_LEAK_OVP}	Leakage current for SBU pins when device is in OVP	VPWR = 0 V or 3.3 V, VC_SBUx = 24 V, SBUx pins are set to 0 V, measure leakage out of SBUx pins	–1		1	µA
I_{Dx_LEAK}	Leakage current for Dx pins	V_Dx = 3.6 V, measure leakage into Dx pins			1	µA
FLT Pin
V_OL	Low-level output voltage	IOL = 3 mA. Measure the voltage at the FLT pin			0.4	V
Over Temperature Protection
T_{SD_RISING}	The rising over-temperature protection shutdown threshold		150	175		°C
T_{SD_FALLING}	The falling over-temperature protection shutdown threshold		130	140		°C
T_{SD_HYST}	The over-temperature protection shutdown threshold hysteresis			35		°C
Dx ESD Protection
V_{RWM_POS}	Reverse stand-off voltage from Dx to GND	Dx to GND. I_DX ≤ 1 µA			5.5	V
V_{RWM_NEG}	Reverse stand-off voltage from GND to Dx	GND to Dx			0	V
V_{BR_POS}	Break-down voltage from Dx to GND	Dx to GND. I_BR = 1 mA	7			V
V_{BR_NEG}	Break-down voltage from GND to Dx	GND to Dx. I_BR = 8 mA	0.6			V
C_IO	Dx to GND or GND to Dx	f = 1 MHz, VIO = 2.5 V		1.7		pF
ΔC_IO	Differential capacitance between two Dx pins	f = 1 MHz, VIO = 2.5 V		0.02		pF
R_DYN	Dynamic on-resistance Dx IEC clamps	Dx to GND or GND to Dx		0.4		Ω

7.7 Timing Requirements

		MIN	NOM	MAX	UNIT
Power-On and Off Timings
t_ON	Time from crossing rising VPWR UVLO until CC and SBU OVP FETs are on			3.5	ms
dV_{PWR_OFF}/dt	Minimum slew rate allowed to guarantee CC and SBU FETs turnoff during a power off	–0.5			V/µs
Over Voltage Protection
t_{OVP_RESPONSE_CC}	OVP response time on the CC pins. Time from OVP asserted until OVP FETs turnoff		70		ns
t_{OVP_RESPONSE_SBU}	OVP response time on the SBU pins. Time from OVP asserted until OVP FETs turnoff		80		ns
t_{OVP_RECOVERY_CC_1}	OVP recovery time on the CC pins. Once an OVP has occurred, the minimum time duration until the CC FETs turn back on. OVP must be removed for CC FETs to turn back on	21	29	39	ms
t_{OVP_RECOVERY_SBU_1}	OVP recovery time on the SBU pins. Once an OVP has occurred, the minimum time duration until the SBU FETs turn back on. OVP must be removed for SBU FETs to turn back on	21	29	39	ms
t_{OVP_RECOVERY_CC_2}	OVP recovery time on the CC pins. Time from OVP removal until CC FET turns back on, if device has been in OVP > 40 ms		0.5		ms
t_{OVP_RECOVERY_SBU_2}	OVP recovery time on the SBU pins. Time from OVP removal until SBU FET turns back on, if device has been in OVP > 40 ms		0.5		ms
t_{OVP_FLT_ASSERTION}	Time from OVP asserted to FLT assertion		20		µs
t_{OVP_FLT_DEASSERTION}	Time from CC FET turnon after an OVP to FLT deassertion		5		ms