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  • TPS564208 4.5-V to 17-V Input, 4-A Synchronous Step-Down Voltage Regulator in SOT-23

    • SLVSDG0B March   2016  – December 2017 TPS564208

      PRODUCTION DATA.  

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  • TPS564208 4.5-V to 17-V Input, 4-A Synchronous Step-Down Voltage Regulator in SOT-23
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adaptive On-Time Control and PWM Operation
      2. 7.3.2 Soft Start and Pre-Biased Soft Start
      3. 7.3.3 Current Protection
      4. 7.3.4 Undervoltage Lockout (UVLO) Protection
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Standby Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Resistors Selection
        3. 8.2.2.3 Output Filter Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Bootstrap Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Development Support
      1. 11.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE
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DATA SHEET

TPS564208 4.5-V to 17-V Input, 4-A Synchronous Step-Down Voltage Regulator in SOT-23

1 Features

  • TPS564208 4-A Converter Integrated 50-mΩ and 22-mΩ FETs
  • D-CAP2™ Mode Control with Fast Transient Response
  • Input Voltage Range: 4.5 V to 17 V
  • Output Voltage Range: 0.76 V to 7 V
  • Continuous Current Mode
  • 560-kHz Switching Frequency
  • Low Shutdown Current Less than 10 µA
  • 1.6% Feedback Voltage Accuracy (25ºC)
  • Startup from Pre-Biased Output Voltage
  • Cycle-by-Cycle Overcurrent Limit
  • Hiccup-mode Overcurrent Protection
  • Non-Latch UVP and TSD Protections
  • Fixed Soft Start: 1.0 ms
  • Create a Custom Design Using the TPS564208 With the WEBENCH® Power Designer

2 Applications

  • Digital TV Power Supply
  • High Definition Blu-ray™ Disc Players
  • Networking Home Terminal
  • Digital Set Top Box (STB)
  • Surveillance

3 Description

The TPS564208 is a simple, easy-to-use, 4-A synchronous step-down converter in SOT-23 package.

The device is optimized to operate with minimum external component count and also optimized to achieve low standby current.

These switch mode power supply (SMPS) devices employ D-CAP2 mode control providing a fast transient response and supporting both low-equivalent series resistance (ESR) output capacitors such as specialty polymer and ultra-low ESR ceramic capacitors with no external compensation components.

The TPS564208 is available in a 6-pin 1.6-mm × 2.9-mm SOT (DDC) package, and specified from a –40°C to 125°C junction temperature.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS564208 DDC (6) 1.60 mm × 2.90 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

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Simplified Schematic

TPS564208 Simplified_Schematic_001_SLVSDG0.gif

TPS564208 Efficiency

TPS564208 D018_SLVSDG0.gif

4 Revision History

Changes from A Revision (October 2017) to B Revision

  • Changed the IVIN MAX value From: 780 µA To: 820 µA in the Electrical Characteristics Go

Changes from * Revision (March 2016) to A Revision

  • Added WEBENCH® Designer link to Features Go
  • Changed VFBTH spec MIN from 739 to 745, TYP from 759 to 760, and MAX from 779 to 775 Go
  • Added Custom Design With WEBENCH® ToolsGo

5 Pin Configuration and Functions

DDC Package
6-Pin SOT
Top View
TPS564208 Pinout_DDC-6_SLVSD90.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
GND 1 — Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller circuit. Connect sensitive VFB to this GND at a single point.
SW 2 O Switch node connection between high-side NFET and low-side NFET.
VIN 3 I Input voltage supply pin. The drain terminal of high-side power NFET.
VFB 4 I Converter feedback input. Connect to output voltage with feedback resistor divider.
EN 5 I Enable input control. Active high and must be pulled up to enable the device.
VBST 6 O Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between VBST and SW pins.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage VIN, EN –0.3 19 V
VBST –0.3 25 V
VBST (10 ns transient) –0.3 27 V
VBST (vs SW) –0.3 6.5 V
VFB –0.3 6.5 V
SW –2 19 V
SW (10 ns transient) –3.5 21 V
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Supply input voltage range 4.5 17 V
VI Input voltage range VBST –0.1 23 V
VBST (10 ns transient) –0.1 26
VBST (vs SW) –0.1 6.0
EN –0.1 17
VFB –0.1 5.5
SW –1.8 17
SW (10 ns transient) –3.5 20
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS564208 UNIT
DDC (SOT)
6 PINS
RθJA Junction-to-ambient thermal resistance 86.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 39.4 °C/W
RθJB Junction-to-board thermal resistance 13.3 °C/W
ψJT Junction-to-top characterization parameter 1.8 °C/W
ψJB Junction-to-board characterization parameter 13.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IVIN Operating – non-switching supply current VIN current, EN = 5 V, VFB = 1 V 640 820 µA
IVINSDN Shutdown supply current VIN current, EN = 0 V 0.9 5 µA
LOGIC THRESHOLD
VENH EN high-level input voltage EN 1.6 V
VENL EN low-level input voltage EN 0.8 V
REN EN pin resistance to GND VEN = 12 V 225 425 900 kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH VFB threshold voltage VO = 1.05 V, continuous mode operation 745 760 775 mV
IVFB VFB input current VFB = 0.8 V 0 ±0.1 µA
MOSFET
RDS(on)h High-side switch resistance TA = 25°C, VBST – SW = 5.5 V 50 mΩ
RDS(on)l Low-side switch resistance TA = 25°C 22 mΩ
CURRENT LIMIT
Iocl Current limit(1) DC current, VOUT = 1.05 V, L1 = 1.5 µH 4.2 6 7.7 A
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold(1) Shutdown temperature 172 °C
Hysteresis 38
ON-TIME TIMER CONTROL
tOFF(MIN) Minimum off time VFB = 0.68 V 220 280 ns
SOFT START
tSS Soft-start time Internal soft-start time 1 ms
FREQUENCY
Fsw Switching frequency VIN = 12 V, VO = 1.05 V, FCCM mode 560 kHz
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VUVP Output UVP threshold Hiccup detect (H > L) 65%
THICCUP_WAIT Hiccup on time 1.9 ms
THICCUP_RE Hiccup time before restart 15.5 ms
UVLO
UVLO UVLO threshold Wake up VIN voltage 4 4.3 V
Shutdown VIN voltage 3.3 3.6
Hysteresis VIN voltage(1) 0.4
(1) Not production tested.

6.6 Typical Characteristics

VIN = 12 V (unless otherwise noted)
TPS564208 D001_SLVSDG0.gif
Figure 1. TPS564208 Supply Current vs Junction Temperature
TPS564208 D003_SLVSDG0.gif
Figure 3. EN Pin UVLO Low Voltage vs Junction Temperature
TPS564208 D005_SLVSDG0.gif
Figure 5. High-Side Rds-On vs Junction Temperature
TPS564208 D007_SLVSDG0.gif
IOUT = 1 A
Figure 7. TPS564208 Switching Frequency vs Input Voltage
TPS564208 D009_SLVSDG0.gif
Figure 9. TPS564208 VOUT = 1.05 V Efficiency, L = 2.2 µH
TPS564208 D011_SLVSDG0.gif
Figure 11. TPS564208 VOUT = 1.8 V Efficiency, L = 2.2 µH
TPS564208 D013_SLVSDG0.gif
Figure 13. TPS564208 VOUT = 5 V Efficiency, L = 3.3 µH
TPS564208 D002_SLVSDG0.gif
Figure 2. VFB Voltage vs Junction Temperature
TPS564208 D004_SLVSDG0.gif
Figure 4. TPS564208 EN Pin UVLO High Voltage vs Junction Temperature
TPS564208 D006_SLVSDG0.gif
Figure 6. Low-Side Rds-On vs Junction Temperature
TPS564208 D008_SLVSDG0.gif
VIN = 12 V
Figure 8. TPS564208 Switching Frequency vs Output Current
TPS564208 D010_SLVSDG0.gif
Figure 10. TPS564208 VOUT = 1.5 V Efficiency, L = 2.2 µH
TPS564208 D012_SLVSDG0.gif
Figure 12. TPS564208 VOUT = 3.3 V Efficiency, L = 2.2 µH

7 Detailed Description

7.1 Overview

The TPS564208 is a 4-A synchronous step-down converter. The proprietary D-CAP2™ mode control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without complex external compensation circuits. The fast transient response of D-CAP2™ mode control can reduce the output capacitance required to meet a specific level of performance.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Adaptive On-Time Control and PWM Operation

The main control loop of the TPS564208 is adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one-shot timer expires. This one shot duration is set inversely proportional to the converter input voltage, VIN, and proportional to the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2TM mode control.

7.3.2 Soft Start and Pre-Biased Soft Start

The TPS564208 has an internal 1.0-ms soft-start. When the EN pin becomes high, the internal soft-start function begins ramping up the reference voltage to the PWM comparator.

If the output capacitor is pre-biased at startup, the device initiates switching and starts ramping up only after the internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the converter ramps up smoothly into regulation point.

7.3.3 Current Protection

The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.

During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN, VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current Iout. If the monitored current is above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.

There are some important considerations for this type of over-current protection. The load current is higher than the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP threshold voltage, the UVP comparator detects it. And then, the device shuts down after the UVP delay time (typically 24 µs) and re-starts after the hiccup time (typically 15.5 ms).

When the over current condition is removed, the output voltage returns to the regulated value.

7.3.4 Undervoltage Lockout (UVLO) Protection

UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage, the device is shut off. This protection is non-latching.

7.3.5 Thermal Shutdown

The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 172°C), the device is shut off. This is a non-latch protection.

7.4 Device Functional Modes

7.4.1 Normal Operation

When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the TPS564208 operates in the normal switching mode. Normal continuous conduction mode (CCM) occurs when the minimum switch current is above 0 A. In CCM, the TPS564208 operates at a quasi-fixed frequency of 560 kHz.

7.4.2 Standby Operation

When the TPS564208 is operating in normal CCM, it may be placed in standby by asserting the EN pin low.

 
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