TLV62569 2-A High Efficiency Synchronous Buck Converter in SOT Package
- SLVSDG1C DECEMBER 2016 – October 2017 TLV62569
  
  UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

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DATA SHEET

TLV62569 2-A High Efficiency Synchronous Buck Converter in SOT Package

1 Features

Up to 95% Efficiency
Low R_DS(ON) Switches 100 mΩ / 60 mΩ
2.5-V to 5.5-V Input Voltage Range
Adjustable Output Voltage from 0.6 V to V_IN
Power Save Mode for Light Load Efficiency
100% Duty Cycle for Lowest Dropout
35-µA Operating Quiescent Current
1.5-MHz Typical Switching Frequency
Power Good Output
Over Current Protection
Internal Soft Startup
Thermal Shutdown Protection
Available in SOT Package
Pin-to-Pin Compatible with TLV62568
Create a Custom Design Using the TLV62569 With the WEBENCH® Power Designer

2 Applications

General Purpose POL Supply
Set Top Box
Network Video Camera
Wireless Router
Hard Disk Driver

3 Description

The TLV62569 device is a synchronous step-down buck DC-DC converter optimized for high efficiency and compact solution size. The device integrates switches capable of delivering an output current up to 2 A.

At medium to heavy loads, the device operates in pulse width modulation (PWM) mode with 1.5-MHz switching frequency. At light load, the device automatically enters Power Save Mode (PSM) to maintain high efficiency over the entire load current range. In shutdown, the current consumption is reduced to less than 2 μA.

The TLV62569 provides an adjustable output voltage via an external resistor divider. An internal soft start circuit limits the inrush current during startup. Other features like over current protection, thermal shutdown protection and power good are built-in. The device is available in a SOT23 and SOT563 package.

Device Information^⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TLV62569DBV	SOT23 (5)	2.90 mm × 2.80 mm
TLV62569PDDC	SOT23 (6)	2.90 mm × 2.80 mm
TLV62569DRL	SOT563 (6)	1.60 mm x 1.60 mm
TLV62569PDRL	SOT563 (6)	1.60 mm x 1.60 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Device Comparison

PART NUMBER	FUNCTION	MARKING SYMBOL
TLV62569DBV	-	16AF
TLV62569PDDC	Power Good	7G
TLV62569DRL	-	19D
TLV62569PDRL	Power Good	19E

Simplified Schematic

TLV62569 TLV62569P typ_app_TLV62569P.gif

Efficiency at 5-V Input Voltage

TLV62569 TLV62569P D008_SLVSDG1_TLV62569.gif

4 Revision History

Changes from B Revision (July 2017) to C Revision

Changed TLV62569DRL and TLV62569PDRL to production statusGo
Added marking symbols for TLV62569DRL and TLV62569PDRL in the Device Comparison tableGo
Added DRL package thermal information Go
Corrected editorial error of EN pin threshold voltageGo
Added current limit for TLV62569DRL and TLV62569PDRL Go
Added TLV62569PDRL layout exampleGo

Changes from A Revision (March 2017) to B Revision

Changed TLV62569PDDC to production status Go
Moved Device Comparison table to page 1Go
Added DDC package thermal informationGo
Added startup time of TLV62569PDDCGo

Changes from * Revision (December 2016) to A Revision

Added WEBENCH® Model Go

5 Pin Configuration and Functions

TLV62569 TLV62569P All_Pinout_TLV62568.gif

Pin Functions

PIN NUMBER				I/O/PWR	DESCRIPTION
NAME	SOT23-5	SOT23-6	SOT563-6	I/O/PWR	DESCRIPTION
EN	1	1	5	I	Device enable logic input. Logic high enables the device, logic low disables the device and turns it into shutdown. Do not leave floating.
GND	2	2	2	PWR	Ground pin.
SW	3	3	4	PWR	Switch pin connected to the internal FET switches and inductor terminal. Connect the inductor of the output filter to this pin.
VIN	4	4	3	PWR	Power supply voltage input.
PG	-	5	6	O	Power good open drain output pin for TLV62569P. The pull-up resistor should not be connected to any voltage higher than 5.5V. If it's not used, leave the pin floating.
FB	5	6	1	I	Feedback pin for the internal control loop. Connect this pin to an external feedback divider.
NC	-	-	6	O	No connection pin for TLV62569DRL. The pin can be connected to the output or the ground. Or leave it floating.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage⁽²⁾	VIN, EN, PG	–0.3	6	V
	SW (DC)	–0.3	V_IN+0.3	V
	SW (AC, less than 10ns)⁽³⁾	–3.0	9	V
	FB	–0.3	5.5	V
Operating junction temperature, T_J		–40	150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and the device is not switching. Functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) While switching

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions⁽¹⁾

		MIN	MAX	UNIT
V_IN	Input voltage	2.5	5.5	V
V_OUT	Output voltage	0.6	V_IN	V
I_OUT	Output current	0	2	A
T_J	Operating junction temperature	–40	125	°C
I_{SINK_PG}	Sink current at PG pin		1	mA

(1) Refer to the Application and Implementation section for further information.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DBV (5 Pins)	DDC (6 Pins)	DRL (6 Pins)	UNIT
R_θJA	Junction-to-ambient thermal resistance	188.2	106.2	146.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	137.5	52.9	51.0	°C/W
R_θJB	Junction-to-board thermal resistance	41.2	31.2	27.0	°C/W
ψ_JT	Junction-to-top characterization parameter	31.4	11.3	2.2	°C/W
ψ_JB	Junction-to-board characterization parameter	40.6	31.6	27.6	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	n/a	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

V_IN = 5.0 V, T_J = 25°C, unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY
I_Q	Quiescent current into VIN pin	Not switching		35		uA
I_SD	Shutdown current into VIN pin	EN = 0 V		0.1	2	µA
V_UVLO	Under voltage lock out	V_IN falling		2.3	2.45	V
V_UVLO	Under voltage lock out hysteresis			100		mV
T_JSD	Thermal shutdown	Junction temperature rising		150		°C
T_JSD	Thermal shutdown	Junction temperature falling		130		°C
LOGIC INTERFACE
V_IH	High-level threshold at EN pin	2.5 V ≤ V_IN ≤ 5.5 V		0.95	1.2	V
V_IL	Low-level threshold at EN pin	2.5 V ≤ V_IN ≤ 5.5 V	0.4	0.85		V
t_SS	Soft startup time	TLV62569DBV		800		µs
t_SS	Soft startup time	TLV62569PDDC, TLV62569DRL, TLV62569PDRL		900		µs
V_PG	Power good threshold	V_FB rising, referenced to V_FB nominal		95%
V_PG	Power good threshold	V_FB falling, referenced to V_FB nominal		90%
V_PG,OL	Power good low-level output voltage	I_SINK = 1 mA			0.4	V
I_PG,LKG	Input leakage current into PG pin	V_PG = 5.0 V		0.01		µA
t_PG,DLY	Power good delay time	V_FB falling		40		µs
OUTPUT
V_FB	Feedback regulation voltage		0.588	0.6	0.612	V
R_DS(on)	High-side FET on resistance			100		mΩ
R_DS(on)	Low-side FET on resistance			60		mΩ
I_LIM	High-side FET current limit	TLV62569DBV, TLV62569PDDC	3			A
I_LIM	High-side FET current limit	TLV62569DRL, TLV62569PDRL	2.5			A
f_SW	Switching frequency	V_OUT = 2.5 V		1.5		MHz

6.6 Typical Characteristics

TLV62569 TLV62569P D001_SLVSDG1_TLV62569.gif

Figure 1. Quiescent Current vs Input Voltage

TLV62569 TLV62569P D003_SLVSDG1_TLV62569.gif

Figure 3. FB Voltage Accuracy

TLV62569 TLV62569P D002_SLVSDG1_TLV62569.gif

Figure 2. Shutdown Current vs Junction Temperature