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The TPSM84A21 and TPSM84A22 are synchronous buck power modules designed to provide up to 10 A of output current. The TPSM84A21 and TPSM84A22 power modules combine the TPS54A20, a 10-A DC/DC synchronous series capacitor buck converter with power MOSFETs, shielded inductors, input and output capacitors, and passive components into a low-profile package. The input voltage range of both devices is 8 V to 14 V. See the Minimum Input Voltage curve in the TPSM84A22, 8-V to 14-V Input, 1.2-V to 2.05-V Output, 10-A SWIFT Power Module Data Sheet for the minimum required input voltage for VOUT > 1.5 V. The output voltage ranges of both devices are given in Table 1-1. The output voltage of the EVM can be set to one of five popular values by using a configuration jumper.
This evaluation module is designed to demonstrate the ease-of-use and small printed-circuit board (PCB) area possible when designing with the TPSM84A21 and TPSM84A22 power modules. Monitoring test points are provided to allow measurement of the following:
Additionally, control test points are provided for use of the power good, inhibit control, and undervoltage lockout features of the device. The EVM uses a recommended PCB layout that maximizes thermal performance and minimizes output ripple and noise.
EVM | Output Voltage Range |
---|---|
TPSM84A21EVM-808 | 0.55 V to 1.3 V |
TPSM84A22EVM-809 | 1.2 V to 2.05 V |
Figure 2-1 highlights the user interface items associated with the EVM. The polarized VIN power terminal block (TB1) is used for connection to the host input supply and the polarized VOUT power terminal block (TB2) is used for connection to the load. These terminal blocks can accept up to 16-AWG wire.
The VIN monitor and VOUT monitor test points located near the power terminal blocks are intended to be used as voltage monitoring points where voltmeters can be connected to measure VIN and VOUT. The voltmeter references should be connected to the PGND test points located beneath the power terminal blocks. Do not use these VIN and VOUT monitoring test points as the input supply or output load connection points. The PCB traces connecting to these test points are not designed to support high currents.
The VIN scope (J1) and VOUT scope (J2) test points can be used to monitor VIN and VOUT waveforms with an oscilloscope. These test points are intended for use with un-hooded scope probes outfitted with a low-inductance ground lead (ground spring) mounted to the scope barrel. The two sockets of each test point are on 0.1-inch centers. The scope probe tip should be connected to the socket labeled VIN or VOUT, and the scope ground lead should be connected to the socket labeled PGND.
The test points located directly below the device are made available to test the features of the device. Any external connections made to these test points should be referenced to one of the PGND test points located along the bottom of the EVM. Refer to Section 3 for more information on the individual control test points.
The VOUT SELECT jumper (P1) is provided for selecting the desired output voltage. Before applying power to the EVM, ensure that the jumper is present and properly positioned for the intended output voltage.
Wire-loop test points and scope probe test points are provided as convenient connection points for digital voltmeters (DVM) or oscilloscope probes to aid in the evaluation of the device. A BNC connector footprint (J3) is available if a synchronization clock is required. Table 3-1 lists a description of each test point.
Pin | Description |
---|---|
VIN | Input voltage monitor. Connect DVM to this point for measuring efficiency. |
VOUT | Output voltage monitor. Connect DVM to this point for measuring efficiency, line regulation, and load regulation. |
PGND | Input and output voltage monitor grounds. Reference the previously mentioned DVMs to any of these four analog ground points. |
VIN Scope (J1) | Input voltage scope monitor. Connect an oscilloscope to this set of points to measure input ripple voltage. |
VOUT Scope (J2) | Output voltage scope monitor. Connect an oscilloscope to this set of points to measure output ripple voltage and transient response. |
EN/UVLO | Connect this point to control ground to disable the device. Allow this point to float to enable the device. An external resistor divider can be connected between this point, control ground, and VIN to adjust the undervoltage lockout of the device. |
PGOOD | Monitors the power good signal of the device. This is an open-drain signal that requires an external pullup resistor if monitoring is desired. A 10- to 100-kΩ pullup resistor is recommended. PWRGD is high if the output voltage is within 95% to 105% of its nominal value. |
SYNC (J3) | Connects to the RT/CLK pin of the device. An external clock signal can be applied to this point to synchronize the device to an appropriate frequency. |
VG | Gate driver supply pin. If supplying an external 5-V supply, connect to this test point. |
Refer to the appropriate product data sheet for absolute maximum ratings associated with the previously-listed features: