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  • High Speed Data Converter Pro GUI

    • SLWU087E november   2013  – june 2023

       

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  • High Speed Data Converter Pro GUI
  1.   1
  2.   High Speed Data Converter Pro GUI
  3.   Trademarks
  4. 1 Introduction
  5. 2 Software Start up
    1. 2.1 Installation Instructions
    2. 2.2 USB Interface and Drivers
    3. 2.3 Device ini Files
  6. 3 User Interface
    1. 3.1 Toolbar
      1. 3.1.1 File Options
        1. 3.1.1.1 User Profiles
        2. 3.1.1.2 Resize Window
      2. 3.1.2 Instrument Options
        1. 3.1.2.1 TSW14J56 and High Speed Data Converter (HSDC) Pro Eye Quality Analysis
        2. 3.1.2.2 IO Delay
        3. 3.1.2.3 JESD204B Error Injection
        4. 3.1.2.4 FPGA Registers Write Read
      3. 3.1.3 Data Capture Option
        1. 3.1.3.1 Capture Option
        2. 3.1.3.2 Trigger Option
        3. 3.1.3.3 Using Multiple TSW14xxx and ADC EVM’s for Simultaneous Capture using Trigger Option
          1. 3.1.3.3.1 Hardware Setup
          2. 3.1.3.3.2 Setting up the Slave Board
          3. 3.1.3.3.3 Setting up the Master Board
          4. 3.1.3.3.4 Read Captured Memory from the Slave Board
      4. 3.1.4 Test Options
        1. 3.1.4.1  Notch Frequency Bins
        2. 3.1.4.2  2 Channel Display and Cursor Lock
        3. 3.1.4.3  Analysis Window Markers
        4. 3.1.4.4  X-Scale in Time
        5. 3.1.4.5  Y-Scale in Voltage
        6. 3.1.4.6  Other Frequency Options
        7. 3.1.4.7  NSD Marker
        8. 3.1.4.8  Phase Plot
        9. 3.1.4.9  Phase in Degree
        10. 3.1.4.10 Histogram
        11. 3.1.4.11 Disable User Popups
        12. 3.1.4.12 HSDC Pro Lite Version
      5. 3.1.5 Help
    2. 3.2 Status Windows
    3. 3.3 Mode Selection
    4. 3.4 Device Selection
    5. 3.5 Skip Configuration
    6. 3.6 Capture Button (ADC Mode Only)
    7. 3.7 Test Selection (ADC Mode only)
      1. 3.7.1 Single Tone FFT
        1. 3.7.1.1 Parameter Controls
        2. 3.7.1.2 ADC Captured Data Display Pane
        3. 3.7.1.3 FFT Power Spectrum
        4. 3.7.1.4 Overlay Unwrap Waveform
        5. 3.7.1.5 Single Tone FFT Statistics
      2. 3.7.2 Multi Channel Display
      3. 3.7.3 Unit Selection
      4. 3.7.4 Time Domain
      5. 3.7.5 Two Tone
      6. 3.7.6 Channel Power
    8. 3.8 DAC Display Panel (DAC Mode only)
      1. 3.8.1 Send Button (DAC Mode Only)
      2. 3.8.2 Load File to Transfer into TSW14xxx Button
      3. 3.8.3 Parameter Controls
    9. 3.9 I/Q Multi-Tone Generator
  7. 4 ADC Data Capture Software Operation
    1. 4.1 Testing a TSW1400 EVM with an ADS5281 EVM
    2. 4.2 Testing a TSW1400EVM with an ADS62P49EVM (CMOS Interface)
  8. 5 TSW1400 Pattern Generator Operation
    1. 5.1 Testing a TSW1400 EVM with a DAC3152 EVM
    2. 5.2 Loading DAC Firmware
    3. 5.3 Configuring TSW1400 for Pattern Generation
    4. 5.4 Testing a TSW1400 EVM with a DAC5688EVM (CMOS Interface)
  9. 6 TSW14J58 Functional Description
    1. 6.1 Testing the TSW14J58 EVM with an ADC12DJ3200 EVM
  10. 7 TSW14J57 Functional Description
    1. 7.1 Testing the TSW14J57 EVM with an ADC34J45 EVM
  11. 8 TSW14J56 Functional Description
    1. 8.1 Testing the TSW14J56 EVM with an ADC34J45 EVM
  12. 9 TSW14J50 Functional Description
    1. 9.1 Device Selection
  13. 10TSW14J10 Functional Description
    1. 10.1 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform
    2. 10.2 DAC38J84EVM GUI Setup Example
  14.   A Signal Processing in High Speed Data Converter Pro
    1.     A.1 Introduction
    2.     A.2 FFT Calculation from Time Domain Data
      1.      A.2.1 FFT Window Correction Factor
    3.     A.3 FFT Filtering
    4.     A.4 Single Tone Parameters
      1.      A.4.1 Number of Neighboring Bins for each FFT Window
    5.     A.5 Fundamental Power
      1.      A.5.1 Harmonic Distortions
      2.      A.5.2 SNR
      3.      A.5.3 SFDR
      4.      A.5.4 THD
      5.      A.5.5 SINAD
      6.      A.5.6 ENOB
      7.      A.5.7 Next Spur
    6.     A.6 Two Tone Parameters
    7.     A.7 Average FFT Calculation
    8.     A.8 NSD Calculation
  15.   B History Notes
  16.   C Revision History
  17. IMPORTANT NOTICE
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User's Guide

High Speed Data Converter Pro GUI

Abstract

This document outlines the High-Speed Data Converter Pro Graphical User Interface (HSDC Pro GUI). Instructions for software start up and the user interface are included. Operating procedures for ADC data capture software and TSW14xxx pattern generation are also provided along with functional descriptions of the TSW1400, TSW1450, and TSW14J5x capture cards.

Trademarks

Xilinx®, Kintex®, UltraScale®, Intel PSG®, and Arria® are registered trademarks of Altera Corporation.

Virtex® are registered trademarks of Xilinx Corporation.

Intel® is a registered trademark of Intel.

All trademarks are the property of their respective owners.

1 Introduction

The HSDC Pro GUI supports testing of all TI high-speed data converter EVMs when used with a TSW14xxx EVM. When used with an ADC EVM, high-speed data (either CMOS, LVDS, JESD204B serial, or JESD204C serial) is captured and then stored into a memory bank or directly inside the FPGA, depending on which TSW14xxx platform is being used. To acquire data on a host PC, the FPGA reads the data from memory and transmits it on Serial Peripheral Interface (SPI). An onboard high-speed USB-to-SPI converter bridges the FPGA SPI interface to the host PC and GUI.

In Pattern Generator Mode, HSDC Pro can generate the desired test patterns or load existing patterns for DAC EVMs under test. These patterns are sent from the host PC over the USB interface to the TSW14xxx. The FPGA stores the data received internally or into board memory, depending on the platform used. The data is then read by the FPGA and transmitted to a DAC EVM across the mating connector.

HSDC Pro GUI uses a DLL and a set of APIs to communicate from the GUI to the TSW14J5x via a Cypress FX3 USB 3.0 device. This next-generation USB 3.0 controller provides a programmable parallel interface which connects directly to the FPGA to provide high speed data transfers. The interface is compatible with both USB 2.0 and 3.0 systems. The theoretical limit for data transfer via USB 3.0 is 5Gbps and USB 2.0 is 480 Mbps. But with packet overhead and handshaking latency the effective throughput via the Cypress FX3 device is 2Gbps for USB 3.0 systems and 320 Mbps for USB 2.0 systems. The samples that are transferred to PC undergoes post processing and is stored as a binary file, due to which the effective data transfer rate is again reduced. With a 3.0 system, the user can capture 1 GBytes ≈ 20 seconds (400 Mbps). With a 2.0 system, around 45 seconds (177 Mbps). This controller is also used to configure the onboard FPGA using parallel programming mode, which allows for configuration in less than three seconds.

For the TSW1400 EVM, the GUI communicates via a FTDI FT4232H device. The FT4232H is a USB 2.0 Hi-Speed to UART IC. It has the capability of being configured in a variety of industry standards, such as serial or parallel interfaces. The FT4232H features 4 UARTs. Two of these have an option to independently configure an MPSSE engine, this allows the FT4232H to operate as two UART/Bit-Bang ports plus two MPSSE engines used to emulate JTAG, SPI, I2C, Bit-bang or other synchronous serial modes.

Key features of the HSDC Pro Software:

  • Single- or multiple-tone frequency tests
  • Continuous data captures
  • Channel power measurement
  • External trigger capability
  • Master and slave operation
  • Pattern generator
  • Load custom patterns
  • Save and export captured data
  • Frequency and Time analysis
  • One GUI supports all TSW14xxx platforms

The TSW14xxx family consists of the following EVMs:

  • TSW1400 – The TSW1400 EVM supports all high-speed ADC and DAC EVMs that use an LVDS or CMOS interface for the data path.
  • TSW14J10 - The TSW14J10 EVM allows users to evaluate TI JESD204B high-speed data converters using existing FPGA vendor development platforms.
  • TSW14J50 – The TSW14J50 EVM supports all high-speed ADC and DAC EVMs using a JESD204B interface for the data path.
  • TSW14J56 – The TSW14J56 EVM supports all high-speed ADC and DAC EVMs using a JESD204B interface for the data path.
  • TSW14J57 – The TSW14J57 EVM supports up to 16 lanes for all high-speed ADC and DAC EVMs using a JESD204B interface for the data path.
  • TSW14J58 - The TSW14J58 EVM supports up to 16 lanes for all high-speed ADC and DAC EVMs using a JESD204C interface for the data path.
  • TSW14DL3200 - The TSW14DL3200 EVM supports up to 48 pairs of high-speed LVDS signals or to provide up to 48 pairs of LVDS data.
  • TSW14J59 - The TSW14J59 EVM supports 24 Gb DDR4 SDRAM (split into two banks of 3 independent 256 × 16, 4 Gb SDRAMs).

Consult the TSW140x High Speed Data Capture/Pattern Generator Card User’s Guide (SLWU079) for more information regarding the hardware aspect of the TSW1400EVM.

Consult the TSW14J5x JESD204B/C High Speed Data Capture and Pattern Generator Card User’s Guide for more information regarding the hardware aspect of these four EVMs.

Consult the TSW14DL3200EVM High Speed LVDS Data Capture/Pattern Generator Card User's Guide for more information regarding the hardware aspect of this EVM.

Consult the TSW14J59EVM JESD204C Data Capture and Pattern Generator Card User's Guide for more information regarding the hardware aspect of this EVM.

Additionally, the user has the option of using Xilinx FPGA development kits to interface with TI's JESD204B based high-speed data converter EVMs.

 
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