Achieving high converter efficiency with an active clamp in a PSFB converter

1 Introduction

Phase-shifted full-bridge (PSFB) converters (see Figure 1-1) are widely applied to high-power applications, mainly because a PSFB converter can achieve soft switching on its input switches and thus facilitate high converter efficiency [1]. Although soft switching greatly reduces switching losses, the output rectifier parasitic capacitance resonates with the transformer leakage inductors – modeled as L_r in Figure 1-1 – resulting in voltage ringing with high voltage stress [2].

The voltage stress of the output rectifier could be as high as 2 x V_IN x N_S/N_P, where N_P and N_S are the transformer’s primary and secondary windings, respectively. Traditionally, applying a passive snubber [2] (such as the resistor-capacitor-diode [RCD] snubber in Figure 1-1) at the output rectifier prevents the rectifier voltage from going too high and enables the use of a lower-voltage-rated component with a better figure of merit for lower power dissipation.

When applying metal-oxide semiconductor field-effect transistors (MOSFETs) as a synchronous rectifier (SR), you can expect lower C_oss and R_DS(on) on lower-voltage-rated MOSFETs at the same cost level compared to higher-voltage-rated MOSFETs. However, using a passive snubber means that part of the energy that caused the voltage ringing will dissipate in the passive snubber and result in an efficiency reduction.

This article introduces an active (rather than a passive) snubber and its related control, which minimizes rectifier voltage stress to achieve higher converter efficiency while also greatly reducing energy dissipation in the snubber circuit and without sacrificing operational range.

Figure 1-1 A PSFB power stage with a passive clamp and key waveforms.

2 A PSFB converter with an active clamp

As shown in Figure 2-1, inserting an active clamp leg formed by a capacitor (C_CL) and a MOSFET (Q_CL) before the output inductor enables active clamp leg current conduction within the effective duty-cycle (D_eff) period, thus clamping the secondary winding voltage (V_SEC) and rectifier voltage stress to the C_CL voltage – V_CL. In order to have low voltage stress on the output rectifier, you must select a large-enough C_CL for low capacitor voltage ripple. A rule of thumb is to select the inductor-capacitor (LC) resonant period formed by L_r and C_CL to be much longer than the switching period (T_s) [3] expressed by Equation 1:

Equation 1. $2 π \sqrt{{(\frac{N_{S}}{N_{P}})}^{2} L_{r} C_{C L}} ≫ T_{S}$

The rectifier voltage stress will clamp to around V_INx N_S/N_P with the active snubber, which is about half of the voltage stress without any clamp circuit.

Unlike a passive snubber, an active snubber doesn’t dissipate the ringing energy on the power resistor. Instead, it circulates the energy in the LC resonant tank as a lossless snubber. When the output winding voltage becomes nonzero, energy will transfer from the primary winding to the secondary winding to energize the output inductor and conduct current through the Q_CL body diode, even if Q_CL isn’t turned on. Turning on Q_CL after its body has already conducted current will ensure zero voltage switching (ZVS) on Q_CL. Therefore, you can expect higher converter efficiency on a PSFB converter with an active snubber over a PSFB converter with a passive snubber in an identical specification.

Figure 2-1 A PSFB power stage with active clamp and key waveforms.

3 Active clamp leg design considerations

With the active snubber implemented in a PSFB, the transformer winding current will no longer rise monotonically during the effective duty cycle (D_eff) period (T_S) (non-zero output winding voltage period) like output inductor current. This is because the active snubber capacitor energy also participates in energizing output inductor rather than solely rely on energy transfer from the input side. The non-monotonic current ramp characteristic could make peak current mode control difficult as input or transformer winding current are generally utilized for peak current detection and higher input or transformer winding current does not necessarily represent larger duty cycle.

In order to allow peak current detection happens when current is rising monotonically, we must ensure D_effT_S is always greater than the duration where current-second balance is completed – D_CSBT_S – under whole operational voltage and load ranges. As high efficiency is expected for a PSFB with larger D_eff, PSFB is generally designed to have larger D_eff at mid-to-heavy load where D_eff >> D_CSB is expected. At light load, converter is expected to operate under discontinuous conduction mode where D_eff will be smaller than D_eff under continuous conduction mode at the same input/output voltage condition. In order to keep D_effT_S greater than D_CSBT_S even at light load, we have implemented frequency reduction control based on load current.

The duration of D_CSBT_S becomes an important factor for peak current mode control. How long does it take to complete current-second balance is now the one-million-dollar question. To answer this question, you’ll need to calculate current flow through the active clamp leg.

Assuming that V_CL is a constant and L_m = ∞, Equation 2 expresses the rectifier current changing rate during the duty-cycle loss period (the period where V_SEC = 0 and i_SR1 and i_SR2 are commuting) as:

Equation 2.

\frac{{∆ i}_{S R}}{∆ t} = \frac{N_{p}}{N_{S}} \frac{V_{L r}}{L_{r}} = \frac{\frac{N_{S}}{N_{P}} V_{I N} - V_{C L}}{{(\frac{N_{S}}{N_{P}})}^{2} L_{r}}

where V_Lr is the voltage across L_r.

Equation 3 calculates the changing rate of the output inductor current:

Equation 3.

\frac{{∆ i}_{L O}}{∆ t} = \frac{V_{C L} - {V O U T}_{}}{L_{o}}

Using Equation 2 and Equation 3 along with Kirchhoff’s current law, Equation 4 calculates the changing rate of the active clamp current:

Equation 4.

{∆ i}_{C L} = {∆ i}_{S R} - {∆ i}_{L o} = [\frac{\frac{N_{S}}{N_{P}} V_{I N} - V_{C L}}{({\frac{N_{S}}{N_{P}}}^{2}) L_{r}} - \frac{V_{C L} - V_{O U T}}{L_{O}}] ∆ t

Since V_CL ≈ V_IN x N_S/N_P [3], you just need to apply the total active clamp leg conduction time as Δt in Equation 4 to solve Δi_CL. However, you still need to know the peak value of i_CL in order to calculate the i_CL root-mean-square (RMS) value. As shown in Figure 3-1, if i_SEC = i_Lo (after charging C_oss to V_CL) at time t₂ and i_SEC = i_SR at time t₃ (start to charge C_CL), Equation 5 derives i_CL,peak as:

Equation 5.

i_{C L, p e a k} = {∆ i}_{C L | t 3 - t 2} = i_{C L | t 3} = (i_{S R} - i_{L O}) |t 3 - (i_{S R} - i_{L O})| t 3 = i_{S E C | t 3} - i_{S R | t 2} = {∆ i}_{S E C | t 3 - t 2} - {2 i}_{S R S | t 2} \approx - {2 i}_{S R S | t 2}

Figure 3-1 Key waveforms around the active clamp current conduction period.

With Equation 6 deriving the i_SR2 value at t₂ as:

Equation 6.

i_{S R 2 | t 2} = \frac{V_{I N}}{{}_{N_{P}}^{N_{S}}{L_{r}}} - (t_{2} - t_{1})

Assuming that the i_SR2 current decreasing rate from t₀ to t₂ is the same, Equation 7 derives the time duration of t₂-t₁ as:

Equation 7.

(t_{2} - t_{1}) = \sqrt{2 C_{O S S} \frac{N_{S} V_{C L} L_{r}}{N_{P} V_{I N}}}

Since C_Lneeds to maintain a current second balance, the sum of areas A1 and A3 will equal area A2.

As shown in Equation 7, SR C_oss controls the peak current on the active clamp leg. If you select a low C_oss SR FET, the active clamp leg RMS current is lower and thus helps improve converter efficiency.

Here are some design guidelines when designing a PSFB converter with an active snubber:

QCL must turn on only after the duty-cycle loss duration in order to avoid CCL energy backflow to the primary side.
QCL must be turn on while the body diode is still conducting current for ZVS.
A longer QCL on time will reduce VCL as well as SR voltage stress, but the QCL RMS current will increase.
A lower SR Coss will not only help reduce the active clamp leg RMS current, but also help reduce SR voltage stress.

The active clamp method isn’t limited to full-bridge rectifiers; it is applicable to other types of rectifiers such as current-doubler [4] or center-taped rectifiers. Figure 3-2 shows a PSFB converter with an active clamp on a center-taped rectifier, which is implemented in the 3-kW Phase-Shifted Full Bridge with Active Clamp Reference Design with >270-W/in³ Power Density.

Figure 3-2 A PSFB converter with active snubbers on a center-taped rectifier.

As shown in Figure 3-3, it is possible to clamp SR voltage stress under 40 V with dual active clamp legs, with negligible clamping loss (very minor conduction loss) at a 250-A load current.

Figure 3-3 Steady-state waveform of a PSFB converter with a center-taped rectifier and active snubbers at a 12-V/3-kW output.

4 Summary

A control method allows PSFB converter to work with active snubber under peak current mode control is discussed in this paper. The active snubber allows lower voltage stress on the output rectifier with negligible power dissipation on the snubber circuit that greatly improves converter efficiency. The current disturbance introduced by the active snubber makes peak current mode control difficult. With the active snubber power switch on-time fixed and frequency reduction control implemented, a high efficiency and peak current controlled PSFB converter can be realized. A 400Vin, 12Vout/3kW PSFB prototype is built with the proposed control method has been verified across whole operational load range with output rectifier voltage stress limited below 40 V at 250A full load.

5 References

Designing a Phase Shifted Zero Voltage Transition (ZVT) Power Converter. Unitrode Power Supply Design Seminar SEM 900, 1993.
Lin, Song-Yi, and Chern-Lin Chen. April 1998. “Analysis and Design for RCD Clamped Snubber Used in Output Rectifier of Phase-Shift Full-Bridge ZVS Converters.” Published in IEEE Transactions on Industrial Electronics 45 (2), pp. 358-359.
Sabate, J.A., V. Vlatkovic, R.B. Ridley, and F.C. Lee. 1991. “High-Voltage, High-Power, ZVS, Full-Bridge PWM Converter Employing an Active Snubber.” Sixth Annual Applied Power Electronics Conference and Exhibition, pp. 158-163.
Texas Instruments: Design Review: 100W, 400kHz, DC/DC Converter With Current Doubler Synchronous Rectification Achieves 92% Efficiency.

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