Advanced processors and system-on-chip (SoC) with integrated point-to-point serial communication or an analog front end (AFE) require a power supply with low output-voltage ripple to maintain signal integrity and improve performance. The output-voltage ripple requirement of the processor’s point-of-load (POL) power supply can be below 2-mV, which is about one-tenth of the ripple for a typical design, putting heavy design constraint on the synchronous buck converter. Since the processor’s output current requirements exceed the capabilities of a linear post-regulator, employing a second-stage filter, a higher switching frequency and additional output capacitance greatly reduce the POL’s ripple. Synchronous-buck converters are available with several different control architectures, each having a unique method to ensure stability when designing for low-ripple voltage. This article compares three different control architectures: externally-compensated voltage-mode, constant on-time and selectable-compensation current-mode to achieve 1-mV output voltage ripple complete with test data using the same electrical specifications and comparison of output voltage ripple, solution size, load transients and efficiency.

Three different power supplies were designed and built to demonstrate the performance of each control mode under similar operating conditions. For each design, the input voltage is 12 V, the output voltage is 1 V and the output current for each device is capable of 15-A. These requirements are typical for powering a high-performance SoC that integrates sensitive analog circuitry, requiring low output voltage ripple.

To bound the filter design and performance expectations, the allowable ripple voltage is ±0.15 percent, or ±1.5 mV (3 mVpp) of the output voltage. Our comparison features three TI DC/DC converters: a 15-A D-CAP3™ buck converter (TPS548A28), a 20-A internally compensated advanced current-mode (ACM) buck converter (TPS543B22) and a 15-A voltage-mode buck converter (TPS56121). We selected output voltage, output current and operating frequencies as close as possible to one another within the converter’s capability to support similar second-stage filter components.

Even with low equivalent series resistance (ESR) ceramic output capacitors, it is not practical to use a buck converter’s inductor and capacitor (LC) output filter to achieve low output voltage ripple. Designers will likely need to use a second-stage LC filter in order to achieve output ripple below 5-mV. For more information about the design of a second-stage filter or the ripple measuring techniques, please see resources section. The value of the inductor of the second-stage filter can be calculated using Equation 1 and solving for L2. The inductor L2 is the second-stage inductor, C1 is the primary-stage output capacitor of the buck converter, and C2 is the second-stage capacitor network. For all three designs, the same second-stage filter was used (as shown in Table 3-1), occupying a circuit board area of 92mm² (as shown in Figure 3-1).

Once the second-stage inductor value (L2) is chosen and the components are assembled, the next step is to re-compensate the DC/DC converter’s control loop with the addition of the second-stage inductance and capacitance to ensure stability. It is important to mention that each control architecture has its own unique technique to re-compensate the control loop after adding the second stage filter, if needed. The output voltage ripple, efficiency penalty and stability of each control architecture were evaluated and then summarized the results.

Pulse-width modulation (PWM) with voltage-mode control architecture is accomplished by comparing a voltage error signal from the output voltage and reference voltage to a constant sawtooth-ramp waveform. The ramp is initiated by a clock signal from an oscillator. The TPS56121 employs externally-compensated, type-3 compensation addressing a double-pole power stage that allows the converter to be re-compensated after the addition of a second-stage filter. Adjusting external resistor and capacitor values after the addition of a second stage filter ensures stability. The output voltage peak-to-peak ripple without an additional filter is 4.8-mV. With the additional filter applied, the output voltage ripple is 1.9-mV (as shown in Figure 4-1). In this case, the TPS56121 design required no loop compensation adjustments to ensure stability. Figure 4-2 shows a load transient waveform with a 10-A load-step, and the output voltage waveform after the implementation of the second-stage filter shows no sign of instability.