One of the most common issues with operational amplifier (op amp) circuits is stability. In this article, I’ll answer three important questions with regards to stability:

• How much phase margin do you need for a reliable design?
• How do you compensate an unstable circuit?
• What drop-in solutions are available for stability issues?

Op-amp loop stability is measured in phase margin, which is the difference in the output signal phase shift from 360 degrees when the output closed-loop gain goes below unity. Some shift is inherent to every op amp (for example, the dominant pole), while additional shift depends on the application and components surrounding the amplifier.

Different rules of thumb recommend 30, 45 or even 60 degrees of phase margin, but how much do you really need to ensure reliable performance? For traditional Miller-compensated op amps, it is possible to simulate typical process variations and observe the resulting impact on phase margin.

Figure 1 approximates the open-loop gain (Aol) and output impedance (Zo) of an op amp with a 1MHz unity-gain bandwidth and Zo = 300Ω. Over process variation, the value of the Miller capacitor (C26) can vary approximately ±30%, and an additional ±30% (approximate) over temperature. This variation gives a total error of ±30% × ±30%, which is the same as ±30% + ±9%, or ±39% variation. Since the value of the Miller capacitor changes the placement of the dominant pole in the Aol of the op amp, this variation can significantly impact the unity-gain bandwidth and phase margin, which is why these specifications are always given as typical values, even for precision amplifiers and high-speed amplifiers.

Figure 1 Open-loop gain and output impedance PSpice® for TI circuit

The amplifier in Figure 1 is set with a load resistance and capacitance so that the feedback loop has 45 degrees of phase margin. Running a Monte Carlo analysis on the dominant factors of the loop stability – the Miller capacitor, open-loop output impedance and passive devices surrounding the amplifier – will show an estimate of how changes over process variation and temperature will impact the phase margin of the circuit.

Figure 2 plots the resulting phase margin. For this analysis, I applied ±40% variation to the Miller capacitor, ±15% variation for Zo, ±10% for the load capacitor and ±5% for the load resistor. These are the expected internal tolerances for the Miller capacitor and Zo, as well as typical component precision for many general-purpose applications.

Figure 2 5,000-run Monte-Carlo analysis across estimated process variation and temperature shifts

Across this variation, the phase margin of the feedback loop sees a minimum phase margin of 19 degrees, a 26 degree shift from 45 degrees. Over process variation and temperature, the circuit would remain stable if it had approximately 27 degrees of phase margin, although 45 degrees will offer both good transient performance and settling time. The closer the phase margin gets to 0 degrees, the more the output will overshoot the final value, and the longer it will take to settle to the final output value. 45 degrees of phase margin provides enough design tolerance to allow a shift in phase margin without compromising settling time or seeing excessive overshoot.

While these simulations are helpful in understanding the effects of Miller capacitor variation on performance, it’s the circuit designer who is ultimately responsible for the performance of their design. Simulations are only as accurate as the included nonidealites, assuming many ideal properties in order to make the calculation less intensive.