DATA SHEET
LMK61PD0A2 Ultra-Low Jitter Pin Selectable Oscillator
1 Features
-
Ultra-low Noise, High Performance
- Jitter: 90 fs RMS typical fOUT > 100 MHz
- PSRR: -70 dBc, robust supply noise immunity
- Flexible Output Frequency and Format; User Selectable
- Frequencies: 62.5 MHz, 100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 312.5 MHz
- Formats: LVPECL, LVDS or HCSL
- Total frequency tolerance of ± 50 ppm
- Internal memory stores multiple start-up configurations, selectable through pin control
- 3.3V operating voltage
- Industrial temperature range (-40ºC to +85ºC)
- 7 mm x 5 mm 8-pin package
2 Applications
- High-performance replacement for crystal-, SAW-, or silicon-based Oscillators
- Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN
- Test and Measurement
- Medical Imaging
- FPGA, Processor Attach
3 Description
The LMK61PD0A2 is an ultra-low jitter PLLatinumTM pin selectable oscillator that generates commonly used reference clocks. The device is pre-programmed in factory to support seven unique reference clock frequencies that can be selected by pin-strapping each of FS[1:0] to VDD, GND or NC (no connect). Output format is selected between LVPECL, LVDS, or HCSL by pin-strapping OS to VDD, GND or NC. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| LMK61PD0A2 | 8-pin QFM (SIA) | 7.0 mm x 5.0 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
Pinout and Simplified Block Diagram
4 Revision History
Changes from * Revision (October 2015) to A Revision
- Product Preview to Production Data Release Go
5 Device Control
Table 1. Output Frequency Mapping for FS[1:0] Selection
| FS1 | FS0 | OUT FREQUENCY (MHz) | RELEVANT STANDARDS |
| 0 | 0 | 100 | PCI Express |
| 0 | NC | 312.5 | 10 Gbps Ethernet |
| 0 | 1 | 125 | 1 Gbps Ethernet |
| NC | 0 | 106.25 | Fiber Channel |
| NC | NC | 156.25 | 10 Gbps Ethernet |
| NC | 1 | 212.5 | Fiber Channel |
| 1 | 0 | 62.5 | 1 Gbps Ethernet |
| 1 | NC | Reserved | n/a |
| 1 | 1 | Reserved | n/a |
Table 2. Output Type Mapping for OS, OE Selection
| OS | OE | OUTPUT TYPE |
| X | 0 | Disabled (PLL functional) |
| 0 | 1 | LVPECL |
| NC | 1 | LVDS |
| 1 | 1 | HCSL |
