SNAS724B
February 2018 – February 2025
LMK05028
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
4.1
Device Start-Up Modes
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Diagrams
5.7
Typical Characteristics
6
Parameter Measurement Information
6.1
Output Clock Test Configurations
7
Detailed Description
7.1
Overview
7.1.1
ITU-T G.8262 (SyncE) Standards Compliance
7.2
Functional Block Diagrams
7.2.1
PLL Architecture Overview
7.2.2
3-Loop Mode
7.2.2.1
PLL Output Clock Phase Noise Analysis in 3-Loop Mode
7.2.3
2-Loop REF-DPLL Mode
7.2.4
2-Loop TCXO-DPLL Mode
7.2.5
PLL Configurations for Common Applications
7.3
Feature Description
7.3.1
Oscillator Input (XO_P/N)
7.3.2
TCXO/OCXO Input (TCXO_IN)
7.3.3
Reference Inputs (INx_P/N)
7.3.4
Clock Input Interfacing and Termination
7.3.5
Reference Input Mux Selection
7.3.5.1
Automatic Input Selection
7.3.5.2
Manual Input Selection
7.3.6
Hitless Switching
7.3.7
Gapped Clock Support on Reference Inputs
7.3.8
Input Clock and PLL Monitoring, Status, and Interrupts
7.3.8.1
XO Input Monitoring
7.3.8.2
TCXO Input Monitoring
7.3.8.3
Reference Input Monitoring
7.3.8.3.1
Reference Validation Timer
7.3.8.3.2
Amplitude Monitor
7.3.8.3.3
Missing Pulse Monitor (Late Detect)
7.3.8.3.4
Runt Pulse Monitor (Early Detect)
7.3.8.3.5
Frequency Monitoring
7.3.8.4
PLL Lock Detectors
7.3.8.5
Tuning Word History
7.3.8.6
Status Outputs
7.3.8.7
Interrupt
7.3.9
PLL Channels
7.3.9.1
PLL Frequency Relationships
7.3.9.2
Analog PLL (APLL)
7.3.9.3
APLL XO Doubler
7.3.9.4
APLL Phase Frequency Detector (PFD) and Charge Pump
7.3.9.5
APLL Loop Filter
7.3.9.6
APLL Voltage Controlled Oscillator (VCO)
7.3.9.6.1
VCO Calibration
7.3.9.7
APLL VCO Post-Dividers (P1, P2)
7.3.9.8
APLL Fractional N Divider (N) With SDM
7.3.9.9
REF-DPLL Reference Divider (R)
7.3.9.10
TCXO/OCXO Input Doubler and M Divider
7.3.9.11
TCXO Mux
7.3.9.12
REF-DPLL and TCXO-DPLL Time-to-Digital Converter (TDC)
7.3.9.13
REF-DPLL and TCXO-DPLL Loop Filter
7.3.9.14
REF-DPLL and TCXO-DPLL Feedback Dividers
7.3.10
Output Clock Distribution
7.3.11
Output Channel Muxes
7.3.11.1
TCXO/Ref Bypass Mux
7.3.12
Output Dividers
7.3.13
Clock Outputs (OUTx_P/N)
7.3.13.1
AC-Differential Output (AC-DIFF)
7.3.13.2
HCSL Output
7.3.13.3
LVCMOS Output (1.8 V, 2.5 V)
7.3.13.4
Output Auto-Mute During LOL or LOS
7.3.14
Glitchless Output Clock Start-Up
7.3.15
Clock Output Interfacing and Termination
7.3.16
Output Synchronization (SYNC)
7.3.17
Zero-Delay Mode (ZDM) Configuration
7.3.18
PLL Cascading With Internal VCO Loopback
7.4
Device Functional Modes
7.4.1
Device Start-Up Modes
7.4.1.1
EEPROM Mode
7.4.1.2
ROM Mode
7.4.2
PLL Operating Modes
7.4.2.1
Free-Run Mode
7.4.2.2
Lock Acquisition
7.4.2.3
Locked Mode
7.4.2.4
Holdover Mode
7.4.3
PLL Start-Up Sequence
7.4.4
Digitally-Controlled Oscillator (DCO) Mode
7.4.4.1
DCO Frequency Step Size
7.4.4.2
DCO Direct-Write Mode
7.4.5
Zero-Delay Mode (ZDM)
7.4.6
Cascaded PLL Operation
7.5
Programming
7.5.1
Interface and Control
7.5.2
I2C Serial Interface
7.5.2.1
I2C Block Register Transfers
7.5.3
SPI Serial Interface
7.5.3.1
SPI Block Register Transfer
7.5.4
Register Map Generation
7.5.5
General Register Programming Sequence
7.5.6
EEPROM Programming Flow
7.5.6.1
EEPROM Programming Using Register Commit (Method #1)
7.5.6.1.1
Write SRAM Using Register Commit
7.5.6.1.2
Program EEPROM
7.5.6.2
EEPROM Programming Using Direct SRAM Writes (Method #2)
7.5.6.2.1
Write SRAM Using Direct Writes
7.5.7
Read SRAM
7.5.8
Read EEPROM
7.5.9
EEPROM Start-Up Mode Default Configuration
7.6
Register Maps
8
Application and Implementation
8.1
Application Information
8.1.1
Device Start-Up Sequence
8.1.2
Power Down (PDN) Pin
8.1.3
Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
8.1.3.1
Mixing Supplies
8.1.3.2
Power-On Reset (POR) Circuit
8.1.3.3
Powering Up From a Single-Supply Rail
8.1.3.4
Power Up From Split-Supply Rails
8.1.3.5
Non-Monotonic or Slow Power-Up Supply Ramp
8.1.4
Slow or Delayed XO Start-Up
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.3
Do's and Don'ts
8.4
Power Supply Recommendations
8.4.1
Power Supply Bypassing
8.5
Layout
8.5.1
Layout Guidelines
8.5.2
Layout Example
8.5.3
Thermal Reliability
9
Device and Documentation Support
9.1
Device Support
9.1.1
Clock Architect
9.1.2
TICS Pro
9.2
Documentation Support
9.2.1
Related Documentation
9.3
Receiving Notification of Documentation Updates
9.4
Support Resources
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
Data Sheet
LMK05028
Low-Jitter Dual-Channel Network Synchronizer Clock With EEPROM