The LP87702K-Q1 has two individual buck converters and one boost converter. The LP87702K-Q1 is OTP programmable, meaning default register values are set in the TI production line to the desired values and it is also possible to control the registers through the I2C after power-up. See the LP877020-Q1 Configuration Guide for details on how to use and configure LP87702K-Q1 through the I2C. The main OTP settings for power rails are listed in Table 1-1.
Group | Description | Bit Name | LP87702K-Q1 |
---|---|---|---|
Device Identification | OTP configuration | OTP_ID | 23h |
Revision for OTP_ID | OTP_REV | 0 | |
BUCK0 | Output voltage | BUCK0_VSET | 1.8 V |
Enable, EN-pin or I2C register | BUCK0_EN_PIN_CTRL, BUCK0_EN | EN1 | |
Force PWM | BUCK0_FPWM | Yes | |
Peak current limit | BUCK0_ILIM | 4 A | |
Maximum load current | N/A | 3 A | |
BUCK1 | Output voltage | BUCK1_VSET | 1.01 V |
Enable, EN-pin or I2C register | BUCK1_EN_PIN_CTRL, BUCK1_EN | EN1 | |
Force PWM | BUCK1_FPWM | Yes | |
Peak current limit | BUCK1_ILIM | 4.5 A | |
Maximum load current | N/A | 3.5 A | |
BOOST | Mode, boost, or bypass | N/A | Boost |
Output voltage | BOOST_VSET | 5 V | |
Enable, EN-pin, or I2C register | BOOST_EN_PIN_CTRL, BOOST_EN | EN1 | |
Peak current limit | BOOST_ILIM | 1.4 A | |
Maximum load current | N/A | 0.6 A | |
VANA | VANA over-voltage threshold | N/A | 4.3 V rising |
The full list of register bits loaded from the OTP memory are shown in LP87702-Q1 Technical Reference Manual.
The power supply design challenges for TI radar processors are described below, and the TI radar processors are addressed in this design.
Table 2-1 provides the recommended supply voltage range specifications for different AWR1843 supply rails. The external supply voltage on this pin should be 1.3 V in case the application uses an internal LDO on a 1.0 V or 1.3 V RF rail. If an internal LDO is not used or bypassed, then an external supply voltage on this pin should be 1.0 V. Often an internal LDO is not used as it increases the AWR internal power dissipation. A special power supply sequencing is not needed, but all the input supply rails should be settled before releasing the reset/power good signal to the AWR device. The CAN PHY may need to be controlled by both the PMIC and AWR to avoid a glitch in case the AWR IO enables the CAN PHY when the 3.3 V AWR rail is ramping but the 1.8 V rail is not active.
Input | Description | Minimum (V) | Nominal (V) | Maximum (V) |
---|---|---|---|---|
VDDIN | 1.2 V digital power supply | 1.14 | 1.2 | 1.32 |
VIN_SRAM | 1.2 V power rail for internal SRAM | 1.14 | 1.2 | 1.32 |
VNWA | 1.2 V power rail for SRAM array back bias | 1.14 | 1.2 | 1.32 |
VIOIN | I/O supply (3.3 V of 1.8 V). All CMOS I/Os would operate on this supply. | 3.15 | 3.3 | 3.45 |
1.71 | 1.8 | 1.89 | ||
VIOIN_18 | 1.8 V supply for CMOS I/O | 1.71 | 1.8 | 1.9 |
VIN_18CLK | 1.8 V supply for clock module | 1.71 | 1.8 | 1.9 |
VIOIN_18IFF | 1.8 V supply for LVDS port | 1.71 | 1.8 | 1.9 |
VIN_13RF1 | 1.3 V analog and RF supply. VIN_13RF1 and VIN_13RF2 could be shorted on the board. | 1.23 | 1.3 | 1.36 |
VIN_13RF2 | ||||
VIN_13RF1 (1 V Internal LDO bypass mode) | 0.95 | 1.0 | 1.05 | |
VIN_13RF2 (1 V Internal LDO bypass mode) | ||||
VIN18BB | 1.8 V analog baseband power supply | 1.71 | 1.8 | 1.9 |
VIN_18VCO | 1.8 V RF VCO supply | 1.71 | 1.8 | 1.9 |
Table 2-2 provides the peak supply current specifications and Table 2-3 provides the average power numbers. The typical supply currents and the average power depends on the application software and chirp configuration.
Supply name | Description | Maximum (mA) |
---|---|---|
VDDIN, VIN_SRAM, VNWA | Total current drawn by all nodes driven by 1.2 V rail. | 1000 |
VIN_13RF1, VIN_13RF2 | Total current drawn by all nodes driven by 1.3 V or 1.0 V rail (2 TX, 4 RX simultaneously).(1) | 2000 |
VIOIN_18, VIN_18CLK, VIOIN_18DIFF, VIN_18BB, VIN_18VCO | Total current drawn by all nodes driven by 1.8 V rail. | 850 |
VIOIN | Total current drawn by all nodes driven by 3.3 V rail. | 50 |
Condition | Description | Typical (W) | ||
---|---|---|---|---|
1.0 V internal LDO bypass mode | 25 % duty cycle | 1TX, 4RX | Use Case: Low power mode, 3.2 MSps complex transceiver, 25 ms frame time, 128 chirps, 128 samples/chirp, 8 μs interchirp time (25 % duty cycle), and DSP active. | 1.3 |
2TX, 4RX | 1.38 | |||
50 % duty cycle | 1TX, 4RX | Use Case: Low power mode, 3.2 MSps complex transceiver, 25 ms frame time, 256 chirps, 128 samples/chirp, 8 μs interchirp time (50 % duty cycle), and DSP active. | 1.77 | |
2TX, 4RX | 1.92 | |||
1.3 V internal LDO enabled mode | 25 % duty cycle | 1TX, 4RX | Use Case: Low power mode, 3.2 MSps complex transceiver, 25 ms frame time, 128 chirps, 128 samples/chirp, 8 μs interchirp time (25 % duty cycle), and DSP active. | 1.4 |
2TX, 4RX | 1.48 | |||
50 % duty cycle | 1TX, 4RX | Use Case: Low power mode, 3.2 MSps complex transceiver, 25 ms frame time, 256 chirps, 128 samples/chirp, 8 μs interchirp time (50 % duty cycle), and DSP active. | 1.94 | |
2TX, 4RX | 2.14 |
1.0 V RF and 1.8 V RF rails have very tight ripple specifications as ripple noise on these two rails affect the RF performance. Ripple on 3.3 V and 1.2 V rails do not directly affect the RF performance, but system level noise coupling could affect the RF performance; hence, it is necessary to minimize the ripple on these rails as well. Switching regulators have a fundamental ripple noise at switching frequency and this needs to be reduced. Table 2-4 provides the AWR device ripple noise specification. This ripple specification assumes a -105 dBc target spur level. If a higher spur can be tolerated based on the system requirements, then the ripple specifications can be relaxed. There is a dB-to-dB correlation between supply ripple and spur level. For example, a 1 dB increase in supply ripple will result in 1 dB increase in spur level.
Frequency (kHz) | RF Rail | VCO/IF Rail | |
---|---|---|---|
1.0 V (Internal LDO bypass) (µVRMS) | 1.3 V (µVRMS) | 1.8 V (µVRMS) | |
137.5 | 7 | 648 | 83 |
275 | 5 | 76 | 21 |
550 | 3 | 22 | 11 |
1100 | 2 | 4 | 6 |
2200 | 11 | 82 | 13 |
4200 | 13 | 93 | 19 |
6600 | 22 | 117 | 29 |