LP877451Q1EVM Evaluation Module
Abstract
The LP87745-Q1 device is designed to meet the power management requirements of the AWR and IWR MMICs in various automotive and industrial radar applications. The device has three step-down DC/DC converters, a 5 V boost converter and a 1.8 V/3.3 V LDO. The LDO is powered from the boost and intended for xWR and peripheral devices IO supply. The device is controlled by an SPI serial interface and by enable signal. The step-down DC/DC converters support programmable switching frequency of 17.6 MHz, 8.8 MHz or 4.4 MHz and have low noise across wide frequency range which enables LDO-free power solution with minimal or no additional passive filtering. LP87745-Q1 device offers flexible external component selection to optimize the solution in terms of performance or cost. The features of the device target safety-relevant applications with system-safety requirements up to ASIL-C level.
This user's guide provides instructions to power up and evaluate LP87745-Q1 device using the LP877451Q1EVM evaluation module (EVM) and software user interface (LP87745-Q1 GUI). By default LP877451Q1EVM has LP877451A1RXVRQ1 device OTP version (17.6 MHz, Low noise use case BOM), but this EVM can also be used to evaluate another OTP device from LP8774x-Q1 product family.
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CAUTION: Hot
surface.
Contact may cause burns. Do not touch! |
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1 Top View with Basic External Connections
Figure 1-1 shows the top-view diagram of the EVM along with basic connections. By default, EVM is configured to power up through VBAT supply through onboard 12 V VIN to 3.3 V VOUT pre-regulator. EVM can also be powered through external 3.3 V supply or through USB port. Please refer to Table 3-2 for the right jumper configuration for each power-supply input.
2 Input, Output Voltages, and Load Current Requirements
LP87745-Q1 device works with 3.3 V input supply and supply is internally monitored for undervoltage (UV) and overvoltage (OV) conditions and hence keep the input supply voltage within 3.3 V +/- 8 % to avoid input supply UV/OV detection. Input power plane to the PMIC has option for additional filtering using L1 and L2 on the bottom side of the PCB.
- If the VBAT/preregulator path is used (default configuration), input supply to the device is already regulated to 3.3 V.
- If external 3.3 V supply is used, ensure that input supply voltage is always within the recommended voltage range and drop across supply path must be considered.
- If EVM is configured to work with USB supply, regulators should not be loaded.
Table 2-1 lists the input and output voltage for each regulator and their maximum load-current requirements. Refer LP87745-Q1 device data sheet for more information about device electrical characteristics and its features.
| Regulator Name | Input Supply Voltage at PMIC Supply Pin | Output Voltage | Maximum Load Current | |
|---|---|---|---|---|
| BUCK1 | 3.04 V - 3.56 V | 1.8 V | 3 A | |
| BUCK2 | 3.04 V - 3.56 V | 1.0 V | 3 A | |
| BUCK3 | 3.04 V - 3.56 V | 1.2 V | 3 A | |
| BOOST | 3.04 V - 3.56 V | 5 V | 0.3 A | |
| VIO_LDO | 5 V (Generated from BOOST) | 3.3 V | 0.150 A | |
If all the regulators are loaded with maximum load current simultaneously, PMIC and PCB can become hot. Make sure that PMIC junction temperature does not exceed 150 °C.
3 Jumpers and connectors
LP877451Q1EVM has many terminal blocks, jumpers and test points to offer certain flexibility to help users to verify the EVM according to their application conditions. However, the EVM is pre-configured with default jumper settings and users can power up the regulators without the need of jumper modifications. Setting these jumpers correctly for the correct function of the EVM is important. Table 3-1 lists all the terminal blocks on the EVM and Table 3-2 lists the jumpers and their functionality. All the terminal blocks are marked with polarity and Pin 1 of test points / jumpers are marked with white dot for identification purpose. To understand more about the jumper functionality, see the schematic diagrams in Section 6.1.
| Terminal Block Number | Terminal Block Name | Description |
|---|---|---|
| J1 | VIN 3.3V | 3.3 V External Input Voltage |
| J17 | VIO_LDO | Terminal block for VIO_LDO Output |
| J18 | BOOST | Terminal block for BOOST Output |
| J24 | BUCK1 | Terminal block for BUCK1 Output |
| J25 | BUCK3 | Terminal block for BUCK3 Output |
| J26 | BUCK2 | Terminal block for BUCK2 Output |
| J30 | J30 | USB Connector |
| J33 | VBAT | 5 V - 20 V Input |
| Jumper/Connector Number | Jumper/Connector Name | Configuration | Description |
|---|---|---|---|
| J2 | WD_DIS | Closed (Default) | Pull down resistor in CS_SPI pin enabled which will disable Q&A watchdog during the PMIC power up. For this to be effective, USB cable should not be connected to the EVM when the PMIC is powered up. If USB cable is connected before PMIC is powered up, USB MCU will drive this pin high (through CS_SPI_WD at J15) during the startup |
| Open | Q&A watchdog not disabled during the PMIC power up | ||
| J3 | EN_PVIN_3V3 | Closed (Default) | Connects PMIC ENABLE pin to PVIN_Bx pins (PVIN_3V3) through a pull up resistor and device gets enabled as soon as 3.3 V is generated/applied |
| Open | If PMIC needs to be enabled through USB/GUI or through pre-regulator PGOOD signal, then this jumper must be kept open | ||
| J4 | PVIN_3V3 | Option 1: Pins 1/3 and 2/4 3V3_PREREG (Default) |
PVIN_3V3 connected to preregulator output. J4-Option-2 must be open and J5 must be open. |
| Option 2: Pins 5/7 and 6/8 3V3_PS |
PVIN_3V3 connected to external 3.3V supply (J1). J4-Option-1 must be open and J5 must be open. |
||
| J5 | 3V3_USB | Open (Default) | Either option from J4 must be used. |
| Closed |
PMIC input supply (PVIN_3V3) is generated from USB supply. J4 jumpers must be open if this jumper is closed. |
||
| J6 | EN_LVPMIC | Option 1: Open (Default) | PMIC Enable signal from 3.3 V Input. J3 must be closed |
| Option 2: Pins 1 and 2 | PMIC Enable signal path from GUI interface. J3 must be open if this Option is used | ||
| Option 3: Pins 2 and 3 | PMIC Enable signal path from pre-regulator PGOOD signal. J3 must be open if this Option is used | ||
| J8 | VIO_SEL | Pins 1 and 2 | 3.3 V supply generated from USB supply |
| Pins 2 and 3 (Default) | 3.3 V VIO supply generated from PMIC VIO_LDO | ||
| J9 | SYNCCLKIN | Pins 1 and 2 | SYNCCLKIN pin connected to MCU clock port (used for testing external clock input signal) |
| J10 | VMON1_SEL | Pins 1 and 2 (Default: open) | VMON1 reference voltage generated from voltage divider on VIO supply |
| Pins 2 and 3 (Default: open) | VMON1 voltage taken from BUCK1 (1.8 V) output | ||
| J12 | nRSTOUT | Pins 1 and 2 (Default) | Connects PMIC nRSTOUT signal to MCU port directly |
| Pins 2 and 3 | Connects PMIC nRSTOUT signal to MCU port through level shifter (series resistors must be mounted if this option is used) | ||
| J13 | VMON1_GPO1 | Pins 1 and 2 (Default: open) | Connects PMIC VMON1 signal to MCU port directly |
| Pins 2 and 3 (Default: open) | Connects PMIC VMON1 signal to MCU port through level shifter (series resistors must be mounted if this option is used) | ||
| J14 | nINT | Pins 1 and 2 (Default) | Connects PMIC nINT signal to MCU port directly |
| Pins 2 and 3 | Connects PMIC nINT signal to MCU port through level shifter (series resistors must be mounted if this option is used) | ||
| J15 | SCLK_SPI | Pins 1 and 2 (Default) | Connects PMIC SCLK_SPI signal to MCU SCLK_SPI port directly |
| Pins 2 and 3 | Connects PMIC SCLK_SPI signal to MCU SCLK_SPI port through a level shifter (series resistors need to be mounted if this option is used) | ||
| SDO_SPI | Pins 1 and 2 (Default) | Connects PMIC SDO_SPI signal to MCU SDO_SPI port directly | |
| Pins 2 and 3 | Connects PMIC SDO_SPI signal to MCU SDO_SPI port through a level shifter (series resistors need to be mounted if this option is used) | ||
| CS_SPI_WD | Pins 1 and 2 (Default) | Connects PMIC CS_SPI signal to MCU CS_SPI port directly | |
| Pins 2 and 3 | Connects PMIC CS_SPI signal to MCU CS_SPI port through a level shifter (series resistors must be mounted if this option is used) | ||
| SDI_SPI | Pins 1 and 2 (Default) | Connects PMIC SDI_SPI signal to MCU SDI_SPI port directly | |
| Pins 2 and 3 | Connects PMIC SDI_SPI signal to MCU SDI_SPI port through a level shifter (series resistors need to be mounted if this option is used) | ||
| J16 | nERR_GPO2 | Pins 1 and 2 (Default) | Connects PMIC nERR_GPO signal to MCU port directly |
| Pins 2 and 3 | Connects PMIC nERR_GPO2 signal to MCU port through level shifter (series resistors must be mounted if this option is used) |
