TMS570LC-SEP Single Event Latch-Up (SEL) Radiation Report
Abstract
The purpose of this study is to characterize the effects of heavy-ion irradiation on the single-event latch-up (SEL) performance of the TMS570LC4357-SEP, Arm® Cortex®-R based microcontroller. Heavy-ions with an LETeff of 48 MeV-cm2/mg were used to irradiate the devices with a fluence of 1 x 107 ions/cm2. The results demonstrate that TMS570LC4357-SEP is SEL-free up to LETeff of 48 MeV-cm2/mg at 125°C.
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1 Introduction
The TMS570LC4357-SEP is a high-performance Arm Cortex-R based microcontroller which has on-chip diagnostic features including: dual CPUs in lockstep, Built-In Self-Test (BIST) logic for CPU, the N2HET coprocessors, and for on-chip SRAMs; ECC protection on the L1 caches, L2 flash, and SRAM memories. The device also supports ECC or parity protection on peripheral memories and loopback capability on peripheral I/Os.
The device integrates two Arm Cortex-R5F floating-point CPUs, operating in lockstep, which offer an efficient 1.66 DMIPS/MHz, and can run up to 300 MHz providing up to 498 DMIPS. The device supports the big-endian [BE32] format.
With integrated safety features and a wide choice of communication and control peripherals, the TMS570LC4357-SEP device is an ideal solution for high-performance real-time control applications with safety critical requirements
https://www.ti.com/product/TMS570LC4357
| Description | Device Information |
|---|---|
| TI Part Number | TMS570LC4357-SEP |
| Device Function | Arm Cortex-R based microcontroller |
| Package | 337 GWT (nFBGA) |
| Technology | 12F021.M7C |
| Exposure Facility | Radiation Effect Facility, Cyclotron Institute, Texas A&M University |
| Heavy Ion Fluence per Run | 1 x 106 - 1 x 107 ions/cm2 |
| Irradiation Temperature | 125°C (for SEL testing) |
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2 SEE Mechanisms
The primary single-event effect (SEE) event of interest in the TMS570LC4357-SEP is the destructive single-event latch-up (SEL). From a risk/impact point of view, the occurrence of an SEL is potentially the most destructive SEE event, and the biggest concern for space applications. The 12F021 (CMOS) process node was used for the TMS570LC4357-SEP. CMOS circuitry introduces a potential for SEL susceptibility. SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and N+ and P+ contacts). The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between the power and ground that persists (is “latched”) until power is removed, or until the device is destroyed by the high-current state. The process modifications applied for the SEL-mitigation were sufficient, as the TMS570LC4357-SEP exhibited no SEL with heavy-ions up to an LETeff of 48 MeV-cm2/mg at a fluence of 1 x 107 ions/cm2 and a chip temperature of 125°C.
This study was performed to evaluate the SEL effects with a bias voltage of VCCAD = 5.25 V; VCCIO = 3.6 V; VCC(core) = 1.32 V supply voltages. Heavy (47Ag) ions with LETeff of 48 MeV-cm2/mg were used to irradiate the devices. Flux of 105 ions/s-cm2 and fluence of 107 ions/cm2 were used during the exposure at 125°C temperature.
Figure 2-1 Functional Block Diagram of
the TMS570LC4357-SEP