SPRADA9
December 2023
AM62P
,
AM62P-Q1
1
ABSTRACT
Trademarks
1
Introduction
1.1
Before Getting Started With the Custom Board Design
1.2
Processor Selection
1.3
Technical Documentation
1.4
Design Documentation
2
Block Diagram
2.1
Constructing the Block Diagram
2.2
Selecting the Boot Mode
2.3
Confirming Pinmux (Pin Multiplexing Capability)
3
Power Supply
3.1
Power Supply Architecture
3.1.1
Integrated Power
3.1.2
Discrete Power
3.2
Power (Supply) Rails
3.2.1
Core Supply
3.2.2
Peripheral Power Supply
3.2.3
Internal LDOs for IO Groups (Processor IO Groups)
3.2.4
Dual-Voltage IOs (Processor IOs)
3.2.5
Dual-Voltage Dynamic Switching IOs
3.2.6
VPP (eFuse ROM Programming Supply)
3.3
Determining Board Power Requirements
3.4
Power Supply Filters
3.5
Power Supply Decoupling and Bulk Capacitors
3.5.1
Note on PDN Target Impedance
3.6
Power Supply Sequencing
3.7
Supply Diagnostics
3.8
Power Supply Monitoring
4
Clocking
4.1
Processor External Clock Inputs
4.1.1
Unused WKUP_LFOSC0
4.1.2
LVCMOS Digital Clock Source
4.1.3
Crystal Selection
4.2
Processor Clock Outputs
5
JTAG (Joint Test Action Group)
5.1
JTAG / Emulation
5.1.1
Configuration of JTAG / Emulation
5.1.2
Implementation of JTAG / Emulation
5.1.3
Connection of JTAG Interface Signals
6
Configuration (Processor) and Initialization (Processor and Device)
6.1
Processor Reset
6.2
Latching of Boot Mode Configuration
6.3
Resetting the Attached Devices
6.4
Watchdog Timer
7
Processor Peripherals
7.1
Selecting Peripherals Across Domains
7.2
Memory (DDRSS)
7.2.1
Processor DDR Subsystem and Device Register Configuration
7.2.2
Calibration Resistor Connection
7.3
Media and Data Storage Interfaces
7.4
Ethernet Interface Using Common Platform Ethernet Switch 3-port Gigabit (CPSW3G)
7.5
Programmable Real-Time Unit Subsystem (PRUSS)
7.6
Universal Serial Bus (USB) Subsystem
7.7
General Connectivity Peripherals
7.8
Display Subsystem (DSS)
7.9
Camera Subsystem (CSI)
7.10
Connection of Processor Power Pins, Unused Peripherals and IOs
7.10.1
External Interrupt (EXTINTn)
7.10.2
Reserved Pins (Signals)
8
Interfacing of Processor IOs ( LVCMOS or Open-Drain or Fail-Safe Type IO Buffers) and Simulations
9
Power Consumption and Thermal Analysis
9.1
Power Estimation
9.2
Maximum Current for Different Supply Rails
9.3
Power Modes
9.4
Thermal Design Guidelines
10
Schematic Design, Capture and Review
10.1
Selection of Components and Values
10.2
Schematic Design and Capture
10.3
Schematics Review
11
Floor Planning, Layout, Routing Guidelines, Board Layers and Simulation
11.1
Escape Routing for PCB Design
11.2
LPDDR4 Design and Layout Guidelines
11.3
High-Speed Differential Signal Routing Guidelines
11.4
Board Layer Count and Stack-up
11.4.1
Simulation Recommendations
11.5
Reference for Steps to be Followed for Running Simulation
12
Device Handling and Assembly
12.1
Soldering Recommendations
12.1.1
Additional References
13
References
13.1
Processor Specific
13.2
Common
14
Terminology
15
Revision History
Application Note
Hardware Design Guide for AM62P / AM62P-Q1 Family of Processors