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The PCB layout designer must balance many different requirements when starting a PCB layout. The first is the board stackup. The AM64x and AM243x devices have a 17.2-mm × 17.2-mm package which has a 0.80-mm pitch ball array of 21×21. To minimize cost, this ball grid is a solid array. Due to the number of rows of signal balls around the periphery, designs must have two routing layers, not counting the top and bottom layers, which can also contain some signal routes. Also, due to the number of power supply rails, there must be two layers dedicated for power planes. Ground planes must be added adjacent to the power planes and adjacent to the outer layers for shielding and controlled impedance routing. High-speed interfaces such as the SERDES and the DDR require ground planes for impedance matching. Due to the higher speeds, ground layers both above and below the DDR signals are recommended. The AM64 GP EVM design connected all of the signal balls and included the additional ground planes. The routing was achieved with 10 layers as shown in Table 1-1.
PCB Layer | Layer Routing, Planes or Pours |
---|---|
Layer 1 | Component pads and signal routing |
Layer 2 | Ground |
Layer 3 | Signal routing(1) |
Layer 4 | Ground |
Layer 5 | Power |
Layer 6 | Power |
Layer 7 | Ground |
Layer 8 | Signal routing(1) |
Layer 9 | Ground |
Layer 10 | Component pads (including most decoupling) and signal routing |
A 10-layer stack-up similar to the one above is needed for relatively dense PCBs. Alternately, the layer count can be reduced, assuming one or more of the following exist:
It is not acceptable to violate routing rules simply to save money on reduced PCB layers or due to limited routing time. All requirements must still be met. Also, creative routing increases design validation time, both in simulation and bench testing. This can be minimized if the layout is similar to one of the AM64x EVM designs.
The AM64x EVM is implemented in a 10-layer stack-up, similar to the one described in Table 1-1. This design has nearly every signal ball routed to circuitry or a connector. This drives the requirement for the full number of layers. Additionally, this board is designed for optimum signal integrity on the high-speed interfaces while limiting the board size. The AM64x EVM is implemented without a High Density Interconnect (HDI) and does not use microvias. All vias on the AM64x EVM pass completely through the board. This complicates the escape from the BGA.
Optimum trace routing will have routes as short as possible with a minimum of cross-over. This requires careful placement of the components around the SoC. Figure 2-1 shows the default arrangement of the signal balls and the power and ground balls. Some of the interfaces can move to other locations due to pin multiplex choices, and there are other interfaces not listed that are exposed through pin multiplex choices. The PCB layout team must analyze the locations of the interfaces used and the associated components or connectors.
Placement of the SoC and some of the components or connectors is also dictated by some of the highest performance interfaces. Additionally, due to the PCB losses at multi-gigabit rates, there are routing distance limits that may also limit component placement.
As indicated above, critical interfaces affect component placement options. When routing begins, these critical interfaces must be routed first. The design team must establish a priority for the different interfaces. Those with higher priority must be completed before implementing those of lower priority. PCB layout teams often waste considerable effort ripping up and re-routing traces for lower priority interfaces when deficiencies are found in the routing of more critical interfaces. Always complete routing for the critical interfaces first.
Table 4-1 lists a recommended priority order for interfaces contained on the AM64x and AM243x families of devices. Individual design requirements may cause this list to change, but this provides a good baseline.
Interface | Routing Priority |
---|---|
PCIe/USB3 | 10 (Highest Priority) |
DDR4/LPDDR4 | 9 |
USB2, OSPI | 8 |
Power distribution | 7 |
RGMII | 6 |
QSPI | 6 |
eMMC | 5 |
Clocks | 5 |
MII / RMII | 4 |
SPI | 4 |
Motor control | 4 |
Analog audio | 3 |
GPMC | 2 |
GPIO | 1 |
UART | 1 |
I2C | 1 (Lowest Priority) |
The placement of most of these should appear obvious. The multi-gigabit SERDES interfaces are the most critical due to their data rate and loss concerns. PCIe is at the top because it is very sensitive to PCB losses. The limited length for these routes might affect the PCB placement of the PCIe connector and the AM64x device. PCIe signals are found on the outer rings of the BGA footprint, allowing the traces to escape from the BGA without vias.
The asynchronous and low-speed interfaces are at the bottom. This leaves the synchronous and source-synchronous interfaces on the top, ordered by data rate. The one surprise may be power distribution. Power distribution is often left to last, but this can then result in poor decoupling performance or current starvation and excessive power supply noise due to insufficient copper to carry the power and ground currents. Space for copper and decoupling must be allocated before routing the middle and low priority interfaces.