J721S2, TDA4VE, TDA4AL, TDA4VL, AM68 Power Estimation Tool
Abstract
The Excel-based J721S2 Power Estimation tool allows users to estimate thermal power based on specified loadings for different components (compute cores and peripherals) of the system-on-chip (SoC). The tool allows the user to pre-populate the various fields (which components are used, and utilization of the major components) from a set of representative use cases. This gives a starting point from which a new use case can be customized to judge the power and loadings of their own use case. The tool provides a breakdown of thermal power at the junction temperature (Tj) entered, and also provides a table of power delivery network (PDN) currents computed for this defined use case at Tj = 125°C or 105°C. The J721S2 Power Estimation tool supports the SOCs (e.g. J721S2, TDA4VE, TDA4AL, TDA4VL, AM68) in the J721S2 family.
The tool gives two power estimates:
- Thermal power estimate: The time constant for heating or cooling an SoC is on the order of seconds or minutes. Because this is the primary use for the tool, the loadings represent the average activity over a duration of seconds or minutes.
- Peak / PDN estimate: The time constant for peak current (power) is on the order of a microsecond. Though a use case (on average) can utilize a given component for say 70%, for windows of time that component is at 100% utilization. The tool’s calculation for Peak / Power Delivery Network (PDN) estimates automatically increases the loading on key intellectual property (IP) that is enabled in order to create the PDN requirements.
Download the tool described in this document from https://www.ti.com/lit/zip/SPRUJ91A.
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1 Contributions to Power
The SoC power is typically considered to have two different components – dynamic power and leakage.
The dynamic power is computed based upon two numbers for the IP – max power and idle power (both scaled to the voltage). The dynamic power is computed as the weighted average of the max and idle power:
- Dynamic power is typically computed as fCV. Consider a clock signal on a pcb that is driven from a CMOS output to a CMOS input. Dynamic power is computed based upon the (a) frequency of the signal – f; (b) the capacitance of the input load and the pcb trace capacitance – C; and (c) the voltage swing of the signal – V.
- Within the tool, the user can select the frequency for some IP as well as the IP’s utilization. The frequency and utilization are obviously linked; as the frequency decreases, the utilization needs to increase to maintain the same activity. Therefore, a function that requires 40% loading on an IP has nearly the same power if the frequency is cut in half and the utilization doubles to 80%.
The leakage power is computed based on voltage, junction temperature, and manufacturing process variation. While the process and voltage have strong effects on the leakage power, the leakage power increases exponentially with Tj
- A CMOS transistor is considered to have two states: (a) ON in which the channel between source and drain is conducting; and (b) OFF in which the channel is non-conductive between the source and the drain. Leakage power arises because the OFF state can allow a trickle of current to cross the channel.
2 How to Use the Tool
The tool has two pages:
- Use Case contains many different components that the user can configure to represent their use case; the use case is shown in Figure 2-1. (The individual largest contributors to the power are in column E.) This sheet also contains 4 buttons that initialize different phases of the estimate.
- Results is a blank sheet into which the results are populated.
