SPRZ412N December 2013 – May 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1
This document describes the known exceptions to the functional specifications (advisories). This document may also contain usage notes. Usage notes describe situations where the device's behavior may not match presumed or documented behavior. This may include behaviors that affect device performance or functional correctness.
NUMBER | TITLE | SILICON REVISIONS AFFECTED | |||
---|---|---|---|---|---|
0 | A | B | C | ||
Section 3.1.1 | PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear | Yes | Yes | Yes | Yes |
Section 3.1.2 | Caution While Using Nested Interrupts | Yes | Yes | Yes | Yes |
Section 3.1.3 | SYS/BIOS: Version Implemented in Device ROM is not Maintained | Yes | Yes | Yes | Yes |
Section 3.1.4 | SDFM: Use Caution While Using SDFM Under Noisy Conditions | Yes | Yes | Yes | Yes |
Section 3.1.5 | McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data is Written to the DX1 Register Without Verifying if the XRDY Bit is in its Ready State (1) | Yes | Yes | Yes | Yes |