SWRS215E
April 2019 – December 2024
CC3235S
,
CC3235SF
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Functional Block Diagrams
5
Device Comparison
5.1
Related Products
6
Pin Configuration and Functions
6.1
Pin Diagram
6.2
Pin Attributes
11
6.3
Signal Descriptions
13
6.4
Pin Multiplexing
6.5
Drive Strength and Reset States for Analog and Digital Multiplexed Pins
6.6
Pad State After Application of Power to Device, Before Reset Release
6.7
Connections for Unused Pins
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Power-On Hours (POH)
7.4
Recommended Operating Conditions
7.5
Current Consumption Summary (CC3235S)
24
25
7.6
Current Consumption Summary (CC3235SF)
27
28
7.7
TX Power Control for 2.4 GHz Band
7.8
TX Power Control for 5 GHz
7.9
Brownout and Blackout Conditions
7.10
Electrical Characteristics for GPIO Pins
33
34
7.11
Electrical Characteristics for Pin Internal Pullup and Pulldown
7.12
WLAN Receiver Characteristics
37
38
7.13
WLAN Transmitter Characteristics
40
41
7.14
WLAN Transmitter Out-of-Band Emissions
43
44
7.15
BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
7.16
Thermal Resistance Characteristics for RGK Package
7.17
Timing and Switching Characteristics
7.17.1
Power Supply Sequencing
7.17.2
Device Reset
7.17.3
Reset Timing
7.17.3.1
nRESET (32kHz Crystal)
52
53
7.17.3.2
nRESET (External 32kHz Clock)
55
7.17.4
Wakeup From HIBERNATE Mode
7.17.5
Clock Specifications
7.17.5.1
Slow Clock Using Internal Oscillator
7.17.5.2
Slow Clock Using an External Clock
60
7.17.5.3
Fast Clock (Fref) Using an External Crystal
62
7.17.5.4
Fast Clock (Fref) Using an External Oscillator
64
7.17.6
Peripherals Timing
7.17.6.1
SPI
7.17.6.1.1
SPI Master
68
7.17.6.1.2
SPI Slave
70
7.17.6.2
I2S
7.17.6.2.1
I2S Transmit Mode
73
7.17.6.2.2
I2S Receive Mode
75
7.17.6.3
GPIOs
7.17.6.3.1
GPIO Output Transition Time Parameters (Vsupply = 3.3V)
78
7.17.6.3.2
GPIO Input Transition Time Parameters
80
7.17.6.4
I2C
82
7.17.6.5
IEEE 1149.1 JTAG
84
7.17.6.6
ADC
86
7.17.6.7
Camera Parallel Port
88
7.17.6.8
UART
7.17.6.9
SD Host
7.17.6.10
Timers
8
Detailed Description
8.1
Overview
8.2
Arm® Cortex®-M4 Processor Core Subsystem
8.3
Wi-Fi® Network Processor Subsystem
8.3.1
WLAN
8.3.2
Network Stack
8.4
Security
8.5
FIPS 140-2 Level 1 Certification
8.6
Power-Management Subsystem
8.7
Low-Power Operating Mode
8.8
Memory
8.8.1
External Memory Requirements
8.8.2
Internal Memory
8.8.2.1
SRAM
8.8.2.2
ROM
8.8.2.3
Flash Memory
8.8.2.4
Memory Map
8.9
Restoring Factory Default Configuration
8.10
Boot Modes
8.10.1
Boot Mode List
8.11
Hostless Mode
9
Applications, Implementation, and Layout
9.1
Application Information
9.1.1
BLE/2.4GHz Radio Coexistence
9.1.2
Antenna Selection
9.1.3
Typical Application
9.2
PCB Layout Guidelines
9.2.1
General PCB Guidelines
9.2.2
Power Layout and Routing
9.2.2.1
Design Considerations
9.2.3
Clock Interface Guidelines
9.2.4
Digital Input and Output Guidelines
9.2.5
RF Interface Guidelines
10
Device and Documentation Support
10.1
Third-Party Products Disclaimer
10.2
Tools and Software
10.3
Firmware Updates
10.4
Device Nomenclature
10.5
Documentation Support
10.6
Related Links
10.7
Support Resources
10.8
Trademarks
10.9
Electrostatic Discharge Caution
10.10
Export Control Notice
10.11
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
12.1
Packaging Information
12.1.1
Packaging Option Addendum
Data Sheet
CC3235S and CC3235SF SimpleLink™ Wi-Fi
®
, Dual-Band, Single-Chip Solution