LM3881 Simple Power Sequencer With Adjustable Timing
- SNVS555D January 2008 – December 2014 LM3881
  
  PRODUCTION DATA.

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DATA SHEET

LM3881 Simple Power Sequencer With Adjustable Timing

1 Features

Easiest Method to Sequence Rails
Power-Up and Power-Down Control
Tiny Footprint
Low Quiescent Current of 80 µA
Input Voltage Range of 2.7 V to 5.5 V
Output Invert Feature
Timing Controlled by Small Value External Capacitor

2 Applications

Security Cameras
Servers
Networking Elements
FPGA Sequencing
Microprocessor and Microcontroller Sequencing
Multiple Supply Sequencing

3 Description

The LM3881 Simple Power Sequencer offers the easiest method to control power up and power down of multiple power supplies (switching or linear regulators). By staggering the start-up sequence, it is possible to avoid latch conditions or large inrush currents that can affect the reliability of the system.

Available in VSSOP-8 package, the Simple Sequencer contains a precision enable pin and three open-drain output flags. When the LM3881 is enabled, the three output flags will sequentially release, after individual time delays, thus permitting the connected power supplies to start up. The output flags will follow a reverse sequence during power down to avoid latch conditions. Time delays are defined using an external capacitor and the output flag states can be inverted by the user.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LM3881	VSSOP (8)	3.00 mm x 3.00 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Typical System Application

4 Revision History

Changes from C Revision (April 2013) to D Revision

Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from B Revision (April 2013) to C Revision

Changed layout of National Data Sheet to TI formatGo

5 Pin Configuration and Functions

VSSOP Package

8-Pin DGK

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
VCC	1	I	Input Supply
EN	2	I	Precision Enable
GND	3	–	Ground
INV	4	I	Output Logic Invert
TADJ	5	O	Timer Adjust
FLAG3	6	O	Open-Drain Output 3
FLAG2	7	O	Open-Drain Output 2
FLAG1	8	O	Open-Drain Output 1

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) ⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
VCC, EN, INV, TADJ, FLAG1, FLAG2, FLAG3 to GND	–0.3	6.0	V
Junction Temperature		150	°C
Lead Temperature (Soldering, 5 s)		260	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

6.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–65	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾		2	kV

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
VCC to GND	2.7	5.5	V
EN, INV, TADJ, FLAG1, FLAG2, FLAG3 to GND	–0.3	VCC + 0.3	V
Junction Temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM3881	UNIT
		DGK
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	224.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	107.6
R_θJB	Junction-to-board thermal resistance	145.3
ψ_JT	Junction-to-top characterization parameter	31.8
ψ_JB	Junction-to-board characterization parameter	143.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted). Minimum and Maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J = 25°C and are provided for reference purposes only. T_J = –40°C to +125°C, V_CC = 3.3 V, unless otherwise specified.

PARAMETER		TEST CONDITIONS	MIN⁽¹⁾	TYP⁽²⁾	MAX⁽¹⁾	UNIT
I_Q	Operating Quiescent Current			80	110	µA
OPEN-DRAIN FLAGS
I_FLAG	FLAGx Leakage Current	V_FLAGx = 3.3 V		0.001	1	µA
V_OL	FLAGx Output Voltage Low	I_FLAGx = 1.2 mA			0.4	V
TIME DELAYS
I_{TADJ_SRC}	TADJ Source Current		4	12	20	µA
I_{TADJ_SNK}	TADJ Sink Current		4	12	20	µA
V_HTH	High Threshold Level		1.0	1.22	1.4	V
V_LTH	Low Threshold Level		0.3	0.5	0.7	V
T_CLK	Clock Cycle	C_ADJ = 10 nF		1.2		ms
T_D1, T_D4	Flag Time Delay		9		10	Clock cycles
T_D2, T_D3, T_D5, T_D6	Flag Time Delay			8		Clock cycles
ENABLE PIN
V_EN	EN Pin Threshold		1.0	1.22	1.5	V
I_EN	EN Pin Pullup Current	V_EN = 0 V		7		µA
INV PIN
V_{IH_INV}	Invert Pin V_IH		90% VCC			V
V_{IL_INV}	Invert Pin V_IL				10% VCC	V

(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).

(2) Typical numbers are at 25°C and represent the most likely parametric norm.

6.6 Typical Characteristics

V_CC = 3.3 V unless otherwise specified.

Figure 1. Quiescent Current vs V_CC

Figure 3. Enable Threshold vs Temperature

Figure 5. Time Delay vs Temperature (C_ADJ = 10 nF Nominal)

Figure 7. FLAG Voltage vs Current

Figure 2. Quiescent Current vs Temperature

Figure 4. Time Delay vs V_IN (C_ADJ = 10 nF Nominal)

Figure 6. V_FLAG vs V_IN (INV Low, R_FLAG = 100 kΩ)