SNAS276G May   2005  – September 2015 LM4550B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Comditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  ADC inputs and Outputs
      2. 8.3.2  Analog Mixing: MIX1
      3. 8.3.3  DAC Mixing and 3D Processing
      4. 8.3.4  Analog Mixing: MIX2
      5. 8.3.5  Stereo Mix
      6. 8.3.6  Stereo Outputs
      7. 8.3.7  Mono Output
      8. 8.3.8  Analog Loopthrough And Digital Loopback
      9. 8.3.9  Resets
      10. 8.3.10 Multiple Codecs
        1. 8.3.10.1 Extended AC Link
        2. 8.3.10.2 Secondary Codec Register Access
          1. 8.3.10.2.1 SLOT 0: TAG bits in Output Frames (Controller to Codec)
          2. 8.3.10.2.2 Extended Audio ID Register (28h): Support for Multiple Codecs
          3. 8.3.10.2.3 CODEC Chaining
    4. 8.4 Device Functional Modes
      1. 8.4.1 Test Modes
    5. 8.5 Programming
      1. 8.5.1 AC Link Serial Interface Protocol
        1. 8.5.1.1 AC Link Output Frame: SDATA_OUT, Controller Output to LM4550B Input
          1. 8.5.1.1.1 SDATA_OUT: Slot 0 - Tag Phase
          2. 8.5.1.1.2 SDATA_OUT: Slot 1 - Read/Write, Control Address
          3. 8.5.1.1.3 SDATA_OUT: Slot 2 - Control Data
          4. 8.5.1.1.4 SDATA_OUT: Slots 3 & 4 - PCM Playback Left/Right Channels
          5. 8.5.1.1.5 SDATA_OUT: Slots 7 & 8 - PCM Playback Left/Right Surround
          6. 8.5.1.1.6 SDATA_OUT: Slots 6 & 9 - PCM Playback (Center/LFE)
          7. 8.5.1.1.7 SDATA_OUT: Slots 5, 10, 11, 12 - Reserved
        2. 8.5.1.2 AC Link Input Frame: SDATA_IN, Controller Input from LM4550B Output
          1. 8.5.1.2.1 SDATA_IN: Slot 0 - Codec/Slot Status Bits
          2. 8.5.1.2.2 SDATA_IN: Slot 1 - Status Address / Slot Request Bits
          3. 8.5.1.2.3 SDATA_IN: Slot 2 - Status Data
          4. 8.5.1.2.4 SDATA_IN: Slot 3 - PCM Record Left Channel
          5. 8.5.1.2.5 SDATA_IN: Slot 4 - PCM Record Right Channel
          6. 8.5.1.2.6 SDATA_IN: Slots 5 to 12 - Reserved
    6. 8.6 Register Maps
      1. 8.6.1  LM4550B Register Map
      2. 8.6.2  Register Descriptions
      3. 8.6.3  Reset Register (00h)
      4. 8.6.4  Master Volume Register (02h)
      5. 8.6.5  Headphone Volume Register (04h)
      6. 8.6.6  Mono Volume Register (06h)
      7. 8.6.7  PC Beep Volume Register (0Ah)
      8. 8.6.8  Mixer Input Volume Registers (Index 0Ch - 18h)
      9. 8.6.9  Record Select Register (1Ah)
      10. 8.6.10 Record Gain Register (1Ch)
      11. 8.6.11 General Purpose Register (20h)
      12. 8.6.12 3D Control Register (22h)
      13. 8.6.13 Power-Down Control / Status Register (26h)
      14. 8.6.14 Extended Audio Id Register (28h)
      15. 8.6.15 Extended Audio Status/control Register (2Ah)
      16. 8.6.16 Sample Rate Control Registers (2Ch, 32h)
      17. 8.6.17 Chain-in Control Register (74h)
      18. 8.6.18 Vendor ID Registers (7Ch, 7Eh)
      19. 8.6.19 Reserved Registers
      20. 8.6.20 Low Power Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Improving System Performance
      2. 9.1.2 Backwards Compatibility
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • AC '97 Rev 2.1 Compliant
  • High Quality Sample Rate Conversion From 4 kHz to 48 kHz in 1 Hz Increments
  • Supports up to 6 DAC Channel Systems With Multiple LM4550Bs or With Other TI LM45xx Codecs
  • Unique TI Chaining Function Shares a Single Controller SDATA_IN Pin Among Multiple Codecs
  • Stereo Headphone Amp With Separate Gain Control
  • TI's 3D Sound Stereo Enhancement Circuitry
  • Advanced Power Management Support
  • External Amplifier Power-Down (EAPD) Control
  • PC Beep Passthrough to Line Out During Initialization or Cold Reset
  • Digital 3.3-V and 5-V Supply Options
  • Extended Temperature: −40°C ≤ TA ≤ 85°C
  • Key specifications
    • Analog Mixer Dynamic Range, 97 dB (Typical)
    • DAC Dynamic Range, 89 dB (Typical)
    • ADC Dynamic Range, 90 dB (Typical)
    • Headphone Amp THD+N at 50 mW, 0.02% (Typical) into 32Ω

2 Applications

  • Desktop PC Audio Systems on PCI Cards, AMR Cards, or With Motherboard Chips Sets Featuring AC Link
  • Portable PC Systems as on MDC Cards, or with a Chipset or Accelerator Featuring AC Link
  • General Audio Frequency Systems Requiring 2, 4 or 6 DAC Channels and/or up to 8 ADC Channels
  • Automotive Telematics

3 Description

The LM4550B device is an audio codec for PC systems which is fully PC99 compliant and performs the analog intensive functions of the AC '97 Rev 2.1 architecture. Using 18-bit Sigma-Delta ADCs and DACs, the LM4550B provides 90 dB of Dynamic Range.

The LM4550B was designed specifically to provide a high quality audio path and provide all analog functionality in a PC audio system. It features full duplex stereo ADCs and DACs and analog mixers with access to 4 stereo and 4 mono inputs.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LM4550B LQFP (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Block Diagram

LM4550B LM4500B-simp_FBD.gif