The LM5046 PWM controller contains all of the features necessary to implement a phase-shifted full-bridge topology power converter using either current mode or voltage mode control. This device is intended to operate on the primary side of an isolated DC-DC converter with input voltage up to 100 V. This highly integrated controller-driver provides dual 2-A high- and low-side gate drivers for the four external bridge MOSFETs, plus control signals for the secondary-side synchronous rectifier MOSFETs. External resistors program the dead-time to enable zero-volt switching of the primary FETs. Intelligent startup of the synchronous rectifiers allows monotonic turnon of the power converter even with prebias load conditions. Additional features include cycle-by-cycle current limiting, hiccup mode restart, programmable soft-start, synchronous rectifier soft-start, and a 2-MHz capable oscillator with synchronization capability and thermal shutdown.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LM5046 | HTSSOP (28) | 9.70 mm x 4.40 mm |
WSON (28) | 5.00 mm x 5.00 mm |
Changes from G Revision (March 2013) to H Revision
Changes from F Revision (March 2013) to G Revision
PIN | I/O | DESCRIPTION | APPLICATION INFORMATION | |||
---|---|---|---|---|---|---|
NAME | 38 PIN TSSOP NO. |
28 PIN TSSOP NO. |
WQFN NO. |
|||
UVLO | 1 | 1 | 25 | I | Line Undervoltage Lockout | An external voltage divider from the power source sets the shutdown and standby comparator levels. When UVLO reaches the 0.4 V threshold the VCC and REF regulators are enabled. At the 1.25 V threshold, the SS pin is released and the controller enters the active mode. Hysteresis is set by an internal current sink that pulls 20 µA from the external resistor divider. |
OVP/OTP | 2 | 2 | 26 | I | Overvoltage Protection | An external voltage divider from the input power supply sets the shutdown level during an over-voltage condition. Alternatively, an external NTC thermistor voltage divider can be used to set the shutdown temperature. The threshold is 1.25 V. Hysteresis is set by an internal current that sources 20 µA of current into the external resistor divider. |
RAMP | 4 | 3 | 27 | I | Input to PWM Comparator | Modulation ramp for the PWM comparator. This ramp can be a signal representative of the primary current (current mode) or proportional to the input voltage (feed-forward voltage mode). This pin is reset to GND at the end of every cycle. |
CS | 6 | 4 | 28 | I | Current Sense Input | If CS exceeds 750 mV the PWM output pulse will be terminated, entering cycle-by-cycle current limit. An internal switch holds CS low for 40 nS after either output switches high to blank leading edge transients. |
SLOPE | 7 | 5 | 1 | O | Slope Compensation Current | A ramping current source from 0 to 100 µA is provided for slope compensation in current mode control. This pin can be connected through an appropriate resistor to the CS pin to provide slope compensation. If slope compensation is not required, SLOPE must be tied to ground. |
COMP | 8 | 6 | 2 | I | Input to the Pulse Width Modulator | An external opto-coupler connected to the COMP pin sources current into an internal NPN current mirror. The PWM duty cycle is at maximum with zero input current, while 1 mA reduces the duty cycle to zero. The current mirror improves the frequency response by reducing the AC voltage across the opto-coupler. |
REF | 9 | 7 | 3 | O | Output of a 5V reference | Maximum output current is 15 mA. Locally decouple with a 0.1µF capacitor. |
RT/SYNC | 10 | 8 | 4 | I | Oscillator Frequency Control and Frequency Synchronization | The resistance connected between RT and AGND sets the oscillator frequency. Synchronization is achieved by AC coupling a pulse to the RT/SYNC pin that raises the voltage at least 1.5 V above the 2 V nominal bias level. |
AGND | 11 | 9 | 5 | I | Analog Ground | Connect directly to the Power Ground. |
RD1 | 12 | 10 | 6 | I | Passive to Active Delay | The resistance connected between RD1 and AGND sets the delay from the falling edge of HO1/SR1 or LO1/SR2 and the rising edge of LO1 or HO1 respectively. |
RD2 | 13 | 11 | 7 | I | Active to Passive Delay | The resistance connected between RD2 and AGND sets the delay from the falling edge of LO2 or HO2 and the rising edge of HO2 or LO2 respectively. |
RES | 16 | 12 | 8 | I | Restart Timer | Whenever the CS pin exceeds the 750 mV cycle-by-cycle current limit threshold, 30 µA current is sourced into the RES capacitor for the remainder of the PWM cycle. If the RES capacitor voltage reaches 1.0 V, the SS capacitor is discharged to disable the HO1, HO2, LO1, LO2 and SR1, SR2 outputs. The SS pin is held low until the voltage on the RES capacitor has been ramped between 2 V and 4 V eight times by 10 µA charge and 5 µA discharge currents. After the delay sequence, the SS capacitor is released to initiate a normal start-up sequence. |
SS | 17 | 13 | 9 | I | Soft-Start Input | An internal 20 µA current source charges the SS pin during start-up. The input to the PWM comparator gradually rises as the SS capacitor charges to steadily increase the PWM duty cycle. Pulling the SS pin to a voltage below 200 mV stops PWM pulses at HO1,2 and LO1,2 and turns off the synchronous rectifier FETs to a low state. |
SSSR | 18 | 14 | 10 | I | Secondary Side Soft-Start | An external capacitor and an internal 20 µA current source set the soft-start ramp for the synchronous rectifiers. The SSSR capacitor charge-up is enabled after the first output pulse and SS > 2 V and Icomp < 800 µA |
SSOFF | 19 | 15 | 11 | I | Soft-Stop Disable | When SS OFF pin is connected to the AGND, the LM5046 soft-stops in the event of a VIN UVLO and Hiccup mode current limit condition. If the SSOFF pin is connected to REF pin, the controller hard-stops on any fault condition. Refer to Table 1 for more details. |
SR2 | 25 | 19 | 15 | O | Synchronous Rectifier Driver | Control output for synchronous rectifier gate. Capable of peak sourcing 100 mA and sinking 400 mA. |
VCC | 27 | 21 | 17 | I | Output of Start-Up Regulator | The output voltage of the start-up regulator is initially regulated to 9.5V. Once the secondary side soft-start (SSSR pin) reaches 1 V, the VCC output is reduced to 7.7 V. If an auxiliary winding raises the voltage on this pin above the regulation set-point, the internal start-up regulator will shutdown, thus reducing the IC power dissipation. |
PGND | 28 | 22 | 18 | I | Power Ground | Connect directly to Analog Ground |
LO1, LO2 | 29, 26 | 23, 20 | 19, 16 | O | Low Side Output Driver | Alternating output of the PWM gate driver. Capable of 1.5A peak source and 2A peak sink current. |
SR1 | 30 | 24 | 20 | O | Synchronous Rectifier Driver | Control output for synchronous rectifier gate. Capable of peak sourcing 100 mA and sinking 400 mA. |
BST1,2 | 33, 22 | 25, 18 | 21, 14 | I | Gate Drive Bootstrap | Bootstrap capacitors connected between BST1, 2 and SW1, 2 provide bias supply for the high side HO1,2 gate drivers. External diodes are required between VCC and BST1,2 to charge the bootstrap capacitors when SW1,2 are low. |
HO1,2 | 34, 21 | 26, 17 | 22, 13 | O | High Side Output Driver | High side PWM outputs capable of driving the upper MOSFET of the bridge with 1.5A peak source and 2A peak sink current. |
HS1,2 | 35, 20 | 27, 16 | 23, 12 | O | Switch Node | Common connection of the high side FET source, low side FET drain and transformer primary winding. |
VIN | 38 | 28 | 24 | I | Input Power Source | Input to the Start-up Regulator. Operating input range is 14 V to 100 V. For power sources outside of this range, the LM5046 can be biased directly at VCC by an external regulator. |
NC | 3, 5, 14, 15, 23, 24, 31, 32, 36, 37 | - | - | - | No Connect |
MIN | MAX | UNIT | |
---|---|---|---|
VIN to GND | –0.3 | 105 | V |
HS to GND(2) | –5 | 105 | V |
BST1/BST2 to GND | –0.3 | 116 | V |
BST1/BST2 to HS1/HS2 | –0.3 | 16 | V |
HO1/HO2 to HS1/HS2(1) | –0.3 | BST1/BST2+0.3 | V |
LO1/LO2/SR1/SR2(1) | –0.3 | VCC+0.3 | V |
VCC to GND | –0.3 | 16 | V |
REF,SSOFF,RT,OVP,UVLO to GND | –0.3 | 7 | V |
RAMP | –0.3 | 7 | V |
COMP | –0.3 | V | |
COMP Input Current | 10 | mA | |
All other inputs to GND(1) | –0.3 | REF+0.3 | V |
Junction Temperature | 150 | °C |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Tstg | Storage temperature range | –55 | 150 | °C | |
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | 2 | kV | |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | 750 | V |
MIN | MAX | UNIT | |
---|---|---|---|
VIN Voltage | 14 | 100 | V |
External Voltage Applied to VCC | 10 | 14 | V |
Junction Temperature | –40 | 125 | °C |
SLOPE | –0.3 | 2 | V |
THERMAL METRIC(1) | LM5046 | UNIT | ||
---|---|---|---|---|
PWP | RSG | |||
28 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | 33.9 | 37.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 18.1 | 21.8 | |
RθJB | Junction-to-board thermal resistance | 15.7 | 10.1 | |
ψJT | Junction-to-top characterization parameter | 0.4 | 0.2 | |
ψJB | Junction-to-board characterization parameter | 15.6 | 10 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.0 | 2.6 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STARTUP REGULATOR (VCC PIN) | ||||||
VCC1 | VCC voltage | ICC= 10 mA (SSSR < 1 V) | 9.3 | 9.6 | 9.9 | V |
VCC2 | VCC voltage | ICC= 10 mA (SSSR > 1 V) | 7.5 | 7.8 | 8.1 | V |
ICC(Lim) | VCC current limit | VCC= 6 V | 60 | 80 | mA | |
ICC(ext) | VCC supply current | Supply current into VCC from an externally applied source. VCC = 10 V | 4.6 | mA | ||
VCC load regulation | ICC from 0 to 50 mA | 35 | mV | |||
VCC(UV) | VCC under-voltage threshold | Positive going VCC | VCC1–0.2 | VCC1–0.1 | V | |
VCC under-voltage threshold | Negative going VCC | 5.9 | 6.3 | 6.7 | V | |
IIN | VIN operating current | 4 | mA | |||
VIN shutdown current | VIN = 20 V, VUVLO = 0 V | 300 | 520 | µA | ||
VVIN = 100 V, VUVLO = 0 V | 350 | 550 | µA | |||
VIN start-up regulator leakage | VCC = 10 V | 160 | µA | |||
VOLTAGE REFERENCE REGULATOR (REF PIN) | ||||||
VREF | REF Voltage | IREF = 0 mA | 4.85 | 5 | 5.15 | V |
REF voltage regulation | IREF = 0 to 10 mA | 25 | 50 | mV | ||
IREF(Lim) | REF current limit | VREF = 4.5 V | 15 | 20 | mA | |
VREFUV | VREF under-voltage threshold | Positive going VREF | 4.3 | 4.5 | 4.7 | V |
Hysteresis | 0.25 | V | ||||
UNDERVOLTAGE LOCK OUT AND SHUTDOWN (UVLO PIN) | ||||||
VUVLO | Under-voltage threshold | 1.18 | 1.25 | 1.32 | V | |
IUVLO | Hysteresis current | UVLO pin sinking current when VUVLO < 1.25 V | 16 | 20 | 24 | µA |
Under-voltage standby enable threshold | UVLO voltage rising | 0.32 | 0.4 | 0.48 | V | |
Hysteresis | 0.05 | V | ||||
VOVP | OVP shutdown threshold | OVP rising | 1.18 | 1.25 | 1.32 | V |
OVP hysteresis current | OVP sources current when OVP > 1.25 V | 16 | 20 | 24 | µA | |
SOFT-START (SS PIN) | ||||||
ISS | SS charge current | VSS = 0 V | 16 | 20 | 24 | µA |
SS threshold for SSSR charge current enable | ICOMP < 800 µA | 1.93 | 2.0 | 2.20 | V | |
SS output low voltage | Sinking 100 µA | 40 | mV | |||
SS threshold to disable switching | 200 | mV | ||||
ISSSR | SSSR charge current | VSS > 2 V, ICOMP < 800 µA | 16 | 20 | 24 | µA |
ISSSR-DIS1 | SSSR discharge current 1 | VUVLO < 1.25 V | 54 | 65 | 75 | µA |
ISSSR-DIS2 | SSSR discharge current 2 | VRES > 1 V | 109 | 125 | 147 | µA |
SSSR output low voltage | Sinking 100 µA | 50 | mV | |||
SSSR threshold to enable SR1/SR2 | 1.2 | V | ||||
CURRENT SENSE INPUT (CS PIN) | ||||||
VCS | Current limit threshold | 0.710 | 0.750 | 0.785 | V | |
CS delay to output | 65 | ns | ||||
CS leading edge blanking | 50 | ns | ||||
RCS | CS sink impedance (clocked) | Internal FET sink impedance | 18 | 45 | Ω | |
SOFT-STOP DISABLE (SS OFF PIN) | ||||||
VIH(min) | SSOFF Input Threshold | 2.8 | V | |||
SSOFF pull down resistance | 200 | kΩ | ||||
CURRENT LIMIT RESTART (RES PIN) | ||||||
RRES | RES pull-down resistance | Termination of hiccup timer | 37 | Ω | ||
VRES | RES hiccup threshold | 1 | V | |||
RES upper counter threshold | 4 | V | ||||
RES lower counter threshold | 2 | V | ||||
IRES-SRC1 | Charge current source 1 | VRES < 1 V, VCS> 750 mV | 30 | µA | ||
IRES-SRC2 | Charge current source 2 | 1 V < VRES < 4 V | 10 | µA | ||
IRES-DIS2 | Discharge current source 1 | VCS < 750 mV | 5 | µA | ||
IRES-DIS2 | Discharge current source 2 | 2 V < VRES < 4 V | 5 | µA | ||
Ratio of time in hiccup mode to time in current limit | VRES > 1 V, Hiccup counter | 147 | ||||
VOLTAGE FEED-FORWARD (RAMP PIN) | ||||||
RAMP sink impedance (Clocked) | 5.5 | 20 | Ω | |||
OSCILLATOR (RT PIN) | ||||||
FSW1 | Frequency (LO1, half oscillator frequency) | RT = 25 kΩ | 185 | 200 | 215 | kHz |
FSW2 | Frequency (LO1, half oscillator frequency) | RT = 10 kΩ | 420 | 480 | 540 | kHz |
DC level | 2.0 | V | ||||
RT sync threshold | 2.8 | 3 | 3.3 | V | ||
ZVS TIMING CONTROL (RD1 & RD2 PINS) | ||||||
TPA | HO1/SR1 turn-off to LO1 turn-on LO1/SR2 turn-off to HO1 turn-on |
RD1 = 20 kΩ | 39 | 65 | 89 | ns |
RD1 = 100 kΩ | 230 | 300 | 391 | ns | ||
TAP | LO2 turn-off to HO2 turn-on HO2 turn-off to LO2 turn-on |
RD2 = 20 kΩ | 27 | 55 | 78 | ns |
RD2 = 100 kΩ | 214 | 300 | 378 | ns | ||
COMP PIN | ||||||
VPWM-OS | COMP current to RAMP offset | VRAMP = 0 V | 680 | 800 | 940 | µA |
VSS-OS | SS to RAMP offset | VRAMP = 0 V | 0.78 | 1.0 | 1.22 | V |
COMP current to RAMP gain | ΔRAMP/ΔICOMP | 2400 | Ω | |||
SS to RAMP gain | ΔSS/ΔRAMP | 0.5 | ||||
COMP current for SSSR charge current enable | VSS > 2 V | 690 | 800 | 915 | µA | |
COMP to output delay | 120 | ns | ||||
Minimum duty cycle | ICOMP = 1 mA | 0 | % | |||
SLOPE COMPENSATION (SLOPE PIN) | ||||||
ISLOPE | Slope compensation current ramp | Peak of RAMP current | 100 | µA | ||
BOOST (BST PIN) | ||||||
VBst uv | BST under-voltage threshold | VBST – VHS rising | 3.8 | 4.7 | 5.6 | V |
Hysteresis | 0.5 | V | ||||
HO1, HO2, LO1, LO2 GATE DRIVERS | ||||||
VOL | Low-state output voltage | IHO/LO = 100 mA | 0.16 | 0.32 | V | |
VOH | High-state output voltage | IHO/LO = 100 mA VOHL = VCC – VLO VOHH = VBST – VHO |
0.27 | 0.495 | V | |
Rise Time | C-load = 1000 pF | 16 | ns | |||
Fall Time | C-load = 1000 pF | 11 | ns | |||
IOHL | Peak Source Current | VHO/LO = 0 V | 1.5 | - | A | |
IOLL | Peak Sink Current | VHO/LO = VCC | 2 | - | A | |
SR1, SR2 GATE DRIVERS | ||||||
VOL | Low-state output voltage | ISR1/SR2 = 10 mA | 0.05 | 0.10 | V | |
VOH | High-state output voltage | ISR1/SR2 = 10 mA, VOH = VREF – VSR |
0.17 | 0.28 | V | |
Rise Time | C-load = 1000 pF | 60 | ns | |||
Fall Time | C-load = 1000 pF | 20 | ns | |||
IOHL | Peak Source Current | VSR = 0 V | 0.1 | - | A | |
IOLL | Peak Sink Current | VSR = VREF | 0.4 | - | A | |
THERMAL | ||||||
TSD | Thermal Shutdown Temp | 160 | °C | |||
Thermal Shutdown Hysteresis | 25 | °C |