LM5104 High-Voltage Half-Bridge Gate Driver With Adaptive Delay

1 Features

Drives Both a High-Side and Low-Side N-Channel MOSFET
Adaptive Rising and Falling Edges With Programmable Additional Delay
Single Input Control
Bootstrap Supply Voltage Range up to 118-V DC
Fast Turnoff Propagation Delay (25 ns Typical)
Drives 1000-pF Loads With 15-ns Rise and Fall Times
Supply Rail Undervoltage Lockout
SOIC and WSON-10 4-mm × 4-mm Package

2 Applications

Current Fed Push-Pull Power Converters
High Voltage Buck Regulators
Active Clamp Forward Power Converters
Half-Bridge and Full-Bridge Converters

3 Description

The LM5104 High-Voltage Gate Driver is designed to drive both the high-side and the low-side N-channel MOSFETs in a synchronous buck configuration. The floating high-side driver can work with supply voltages up to 100 V. The high-side and low-side gate drivers are controlled from a single input. Each change in state is controlled in an adaptive manner to prevent shoot-through issues. In addition to the adaptive transition timing, an additional delay time can be added, proportional to an external setting resistor. An integrated high-voltage diode is provided to charge high-side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high-side gate driver. Undervoltage lockout is provided on both the low-side and the high-side power rails. This device is available in the standard SOIC and the WSON packages.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LM5104	SOIC (8)	4.90 mm × 3.91 mm
LM5104	WSON (10)	4.00 mm × 4.00 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Block Diagram

4 Revision History

Changes from C Revision (March 2013) to D Revision

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from B Revision (March 2013) to C Revision

Changed layout of National Data Sheet to TI formatGo

5 Pin Configuration and Functions

D Package

8-Pin SOIC

Top View

DPR Package

10-Pin WSON

Top View

Pin Functions

PIN		NAME	DESCRIPTION	APPLICATION INFORMATION
SOIC	WSON	NAME	DESCRIPTION	APPLICATION INFORMATION
1	1	V_DD	Positive gate drive supply	Locally decouple to V_SS using ESR/ESL capacitor, located as close to IC as possible.
2	2	HB	High-side gate driver bootstrap rail	Connect the positive terminal to bootstrap capacitor to the HB pin and connect negative terminal to HS. The Bootstrap capacitor should be placed as close to IC as possible
3	3	HO	High-side gate driver output	Connect to gate of high-side MOSFET with short low inductance path.
4	4	HS	High-side MOSFET source connection	Connect to bootstrap capacitor negative terminal and source of high-side MOSFET.
5	7	RT	Deadtime programming pin	Resistor from RT to ground programs the deadtime between high- and low-side transitions. The resistor should be located close to the IC to minimize noise coupling from adjacent traces.
6	8	IN	Control input	Logic 1 equals High-side ON and Low-side OFF. Logic 0 equals High-side OFF and Low-side ON.
7	9	V_SS	Ground return	All signals are referenced to this ground.
8	10	LO	Low-side gate driver output	Connect to the gate of the low-side MOSFET with a short low inductance path.

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾⁽¹⁾

	MIN	MAX	UNIT
V_DD to V_SS	–0.3	18	V
V_HB to V_HS	–0.3	18	V
IN to V_SS	–0.3	V_DD + 0.3	V
LO Output	–0.3	V_DD + 0.3	V
HO Output	V_HS – 0.3	V_HB + 0.3	V
V_HS to V_SS	−1	100	V
V_HB to V_SS		118	V
RT to V_SS	–0.3	5	V
Junction Temperature		150	°C
Storage temperature range, T_stg	–55	150	°C

(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

	MIN	MAX	UNIT
V_DD	9	14	V
HS	–1	100	V
HB	V_HS + 8	V_HS + 14	V
HS Slew Rate		< 50	V/ns
Junction Temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM5104		UNIT
		D	DPR
		8 PINS	10 PINS
R_θJA	Junction-to-ambient thermal resistance	114.5	37.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	61.1	38.1
R_θJB	Junction-to-board thermal resistance	55.6	14.9
ψ_JT	Junction-to-top characterization parameter	9.7	0.4
ψ_JB	Junction-to-board characterization parameter	54.9	15.2
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	4.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

MIN and MAX limits apply over the full operating junction temperature range. Unless otherwise specified, T_J = +25°C, V_DD = V_HB = 12 V, V_SS = V_HS = 0 V, RT = 100kΩ. No Load on LO or HO.

	PARAMETER	TEST CONDITIONS	MIN⁽²⁾	TYP	MAX⁽²⁾	UNIT
SUPPLY CURRENTS
I_DD	V_DD Quiescent Current	LI = HI = 0 V		0.4	0.6	mA
I_DDO	V_DD Operating Current	f = 500 kHz		1.9	3	mA
I_HB	Total HB Quiescent Current	LI = HI = 0 V		0.06	0.2	mA
I_HBO	Total HB Operating Current	f = 500 kHz		1.3	3	mA
I_HBS	HB to V_SS Current, Quiescent	V_HS = V_HB = 100 V		0.05	10	µA
I_HBSO	HB to V_SS Current, Operating	f = 500 kHz		0.08		mA
INPUT PINS
V_IL	Low Level Input Voltage Threshold		0.8	1.8		V
V_IH	High Level Input Voltage Threshold			1.8	2.2	V
R_I	Input Pulldown Resistance		100	200	500	kΩ
TIME DELAY CONTROLS
V_RT	Nominal Voltage at RT		2.7	3	3.3	V
I_RT	RT Pin Current Limit	RT = 0 V	0.75	1.5	2.25	mA
T_D1	Delay Timer, RT = 10 kΩ		58	90	130	ns
T_D2	Delay Timer, RT = 100 kΩ		140	200	270	ns
UNDER VOLTAGE PROTECTION
V_DDR	V_DD Rising Threshold		6.0	6.9	7.4	V
V_DDH	V_DD Threshold Hysteresis			0.5		V
V_HBR	HB Rising Threshold		5.7	6.6	7.1	V
V_HBH	HB Threshold Hysteresis			0.4		V
BOOT STRAP DIODE
V_DL	Low-Current Forward Voltage	I_VDD-HB = 100 µA		0.60	0.9	V
V_DH	High-Current Forward Voltage	I_VDD-HB = 100 mA		0.85	1.1	V
R_D	Dynamic Resistance	I_VDD-HB = 100 mA		0.8	1.5	Ω
LO GATE DRIVER
V_OLL	Low-Level Output Voltage	I_LO = 100 mA		0.25	0.4	V
V_OHL	High-Level Output Voltage	I_LO = –100 mA V_OHL = V_DD – V_LO		0.35	0.55	V
I_OHL	Peak Pullup Current	V_LO = 0 V		1.6		A
I_OLL	Peak Pulldown Current	V_LO = 12 V		1.8		A
HO GATE DRIVER
V_OLH	Low-Level Output Voltage	I_HO = 100 mA		0.25	0.4	V
V_OHH	High-Level Output Voltage	I_HO = –100 mA, V_OHH = V_HB – V_HO		0.35	0.55	V
I_OHH	Peak Pullup Current	V_HO = 0 V		1.6		A
I_OLH	Peak Pulldown Current	V_HO = 12 V		1.8		A

6.6 Switching Characteristics

MAX limits apply over the full operating junction temperature range. Unless otherwise specified, T_J = +25°C, V_DD = V_HB = 12 V, V_SS = V_HS = 0 V, No Load on LO or HO .

	PARAMETER	TEST CONDITIONS	TYP	MAX⁽²⁾	UNIT
t_LPHL	Lower Turn-Off Propagation Delay (IN Rising to LO Falling)		25	56	ns
t_HPHL	Upper Turn-Off Propagation Delay (IN Falling to HO Falling)		25	56
t_RC, t_FC	Either Output Rise/Fall Time	C_L = 1000 pF	15
t_R, t_F	Either Output Rise/Fall Time (3V to 9V)	C_L = 0.1 µF	0.6		µs
t_BS	Bootstrap Diode Turn-Off Time	I_F = 20 mA, I_R = 200 mA	50		ns

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Recommended Operating Conditions under which operation of the device is specified. Recommended Operating Conditions do not imply performance limits. For performance limits and associated test conditions, see Electrical Characteristics.

(2) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).