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  • LM5107 100V / 1.4-A Peak Half Bridge Gate Driver

    • SNVS333F November   2004  – September 2016 LM5107

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • LM5107 100V / 1.4-A Peak Half Bridge Gate Driver
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start-up and UVLO
      2. 7.3.2 Level Shift
      3. 7.3.3 Bootstrap Diode
      4. 7.3.4 Output Stages
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD capacitor
        2. 8.2.2.2 Select External Bootstrap Diode and Resistor
        3. 8.2.2.3 Select Gate Driver Resistor
      3. 8.2.3 Power Dissipation
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • D|8
    • MSOI002K
  • NGT|8
    • MPDS406A
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  • snvs333f_pm
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DATA SHEET

LM5107 100V / 1.4-A Peak Half Bridge Gate Driver

1 Features

  • Drives Both a High Side and Low Side N-Channel MOSFET
  • High Peak Output Current (1.4-A Sink / 1.3-A Source)
  • Independent TTL Compatible Inputs
  • Integrated Bootstrap Diode
  • Bootstrap Supply Voltage to 118 V DC
  • Fast Propagation Times (27-ns Typical)
  • Drives 1000 pF Load With 15-ns Rise and Fall Times
  • Excellent Propagation Delay Matching (2-ns Typical)
  • Supply Rail Undervoltage Lockout
  • Low Power Consumption
  • Pin Compatible With ISL6700
  • Packages:
    • SOIC
    • WSON (4 mm x 4 mm)

2 Applications

  • Current Fed Push-Pull Converters
  • Half and Full Bridge Power Converters
  • Solid State Motor Drives
  • Two Switch Forward Power Converters

3 Description

The LM5107 is a low cost high voltage gate driver, designed to drive both the high side and the low side N-Channel MOSFETs in a synchronous buck or a half bridge configuration. The floating high-side driver is capable of working with rail voltages up to 100-V. The outputs are independently controlled with TTL compatible input thresholds. An integrated on chip high voltage diode is provided to charge the high side gate drive bootstrap capacitor. A robust level shifter technology operates at high speed while consuming low power and providing clean level transitions from the control input logic to the high side gate driver. Undervoltage lockout is provided on both the low side and the high side power rails. The device is available in the SOIC and the thermally enhanced WSON packages.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LM5107 SOIC (8) 4.90 mm × 3.91 mm
WSON (8) 4.00 mm × 4.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Block Diagram

LM5107 20130001.gif

4 Revision History

Changes from E Revision (March 2016) to F Revision

  • Changed Thermal Information tableGo
  • Added Overview and Device Functional Modes in Detailed Description sectionGo
  • Deleted HS Transient Voltages Below Ground from Application Information sectionGo
  • Added Typical Application section. Go
  • Added Power Supply Recommendations section. Go
  • Added Receiving Notification of Documentation Updates sectionGo

Changes from D Revision (March 2013) to E Revision

  • Added Device Information table, ESD Ratings, Pin Configuration and Functions section, Detailed Description section, Application and Implementation section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go

Changes from C Revision (March 2013) to D Revision

  • Changed layout of National Semiconductor Data Sheet to TI formatGo

5 Pin Configuration and Functions

D and NGT Packages
8-Pin SOIC, WSON
Top View
LM5107 20130002.gif

Pin Functions

PIN DESCRIPTIONunder APPLICATION INFORMATION
NO. NAME
SOIC WSON(1)
1 1 VDD Positive gate drive supply Locally decouple to VSS using low ESR/ESL capacitor located as close to IC as possible.
2 2 HI High side control input The LM5107 HI input is compatible with TTL input thresholds. Unused HI input should be tied to ground and not left open
3 3 LI Low side control input The LM5107 LI input is compatible with TTL input thresholds. Unused LI input should be tied to ground and not left open.
4 4 VSS Ground reference All signals are referenced to this ground.
5 5 LO Low side gate driver output Connect to the gate of the low side N-MOS device.
6 6 HS High side source connection Connect to the negative terminal of the bootstrap capacitor and to the source of the high side N-MOS device.
7 7 HO High side gate driver output Connect to the gate of the low side N-MOS device.
8 8 HB High side gate driver positive supply rail Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal of the bootstrap capacitor to HS. The bootstrap capacitor should be placed as close to IC as possible.
(1) For WSON package it is recommended that the exposed pad on the bottom of the LM5107 be soldered to ground plane on the PCB board and the ground plane should extend out from underneath the package to improve heat dissipation.

6 Specifications

6.1 Absolute Maximum Ratings

See (1)(2)
MIN MAX UNIT
VDD to VSS -0.3 18 V
HB to HS -0.3 18 V
LI or HI to VSS -0.3 VDD +0.3 V
LO to VSS -0.3 VDD +0.3 V
HO to VSS VHS − 0.3 VHB + 0.3 V
HS to VSS(3) −5 100 V
HB to VSS 118 V
TJ Junction Temperature -40 150 °C
Tstg Storage Temperature Range −55 150 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD = 10V, the negative transients at HS must not exceed -5V.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM)(1) ±2000 V
(1) The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Pin 6 , Pin 7 and Pin 8 are rated at 500V.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD 8 14 V
HS(1) −1 V to 100 V
HB VHS + 8 VHS + 14 V
HS Slew Rate < 50 V/ns
Junction Temperature −40 125 °C
(1) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD = 10V, the negative transients at HS must not exceed -5V.

6.4 Thermal Information

THERMAL METRIC(1) LM5107 UNIT
D (SOIC) NGT (WSON)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance (2) 109.6 38.9(3) °C/W
RθJC(top) Junction-to-case (top) thermal resistance 51.7 37.5 °C/W
RθJB Junction-to-board thermal resistance 50.4 15.9 °C/W
ψJT Junction-to-top characterization parameter 8.1 0.4 °C/W
ψJB Junction-to-board characterization parameter 49.8 16.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 5 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application report.
(2) The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions.
(3) 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power planes embedded in PCB. See AN-1187 Leadless Leadframe Package (LLP) (SNOA401).

6.5 Electrical Characteristics

Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO. Typical limits are for TJ = +25°C, and minimum and maximum limits apply over the operating junction temperature range (–40°C to +125°C).
PARAMETER TEST CONDITIONS MIN(1) TYP MAX(1) UNIT
SUPPLY CURRENTS
IDD VDD Quiescent Current LI = HI = 0V 0.3 0.6 mA
IDDO VDD Operating Current f = 500 kHz 2.1 3.4 mA
IHB Total HB Quiescent Current LI = HI = 0V 0.06 0.2 mA
IHBO Total HB Operating Current f = 500 kHz 1.6 3 mA
IHBS HB to VSS Current, Quiescent VHS = VHB = 100V 0.1 10 µA
IHBSO HB to VSS Current, Operating f = 500 kHz 0.5 mA
INPUT PINS LI and HI
VIL Low Level Input Voltage Threshold 0.8 1.8 V
VIH High Level Input Voltage Threshold 1.8 2.2 V
RI Input Pulldown Resistance 100 180 500 kΩ
UNDER VOLTAGE PROTECTION
VDDR VDD Rising Threshold VDDR = VDD - VSS 6 6.9 7.4 V
VDDH VDD Threshold Hysteresis 0.5 V
VHBR HB Rising Threshold VHBR = VHB - VHS 5.7 6.6 7.1 V
VHBH HB Threshold Hysteresis 0.4 V
BOOT STRAP DIODE
VDL Low-Current Forward Voltage IVDD-HB = 100 µA
VDL = VDD - VHB		 0.58 0.9 V
VDH High-Current Forward Voltage IVDD-HB = 100 mA
VDH = VDD - VHB		 0.82 1.1 V
RD Dynamic Resistance IVDD-HB = 100 mA 0.8 1.5 Ω
LO GATE DRIVER
VOLL Low-Level Output Voltage ILO = 100 mA
VOHL = VLO – VSS		 0.28 0.45 V
VOHL High-Level Output Voltage ILO = −100 mA,
VOHL = VDD– VLO		 0.45 0.75 V
IOHL Peak Pullup Current VLO = 0V 1.3 A
IOLL Peak Pulldown Current VLO = 12V 1.4 A
HO GATE DRIVER
VOLH Low-Level Output Voltage IHO = 100 mA
VOLH = VHO– VHS		 0.28 0.45 V
VOHH High-Level Output Voltage IHO = −100 mA
VOHH = VHB– VHO		 0.45 0.75 V
IOHH Peak Pullup Current VHO = 0V 1.3 A
IOLH Peak Pulldown Current VHO = 12V 1.4 A
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

6.6 Switching Characteristics

Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO. Typical limits are for TJ = +25°C, and minimum and maximum limits apply over the operating junction temperature range (–40°C to +125°C).
Parameter CONDITIONS MIN(1) TYP MAX(1) UNIT
tLPHL Lower Turn-Off Propagation Delay
(LI Falling to LO Falling)		 27 56 ns
tHPHL Upper Turn-Off Propagation Delay
(HI Falling to HO Falling)		 27 56 ns
tLPLH Lower Turn-On Propagation Delay
(LI Rising to LO Rising)		 29 56 ns
tHPLH Upper Turn-On Propagation Delay
(HI Rising to HO Rising)		 29 56 ns
tMON Delay Matching: Lower Turn-On and Upper Turn-Off 2 15 ns
tMOFF Delay Matching: Lower Turn-Off and Upper Turn-On 2 15 ns
tRC, tFC Either Output Rise/Fall Time CL = 1000 pF 15 – ns
tPW Minimum Input Pulse Width that Changes the Output 50 ns
tBS Bootstrap Diode Turn-Off Time IF = 100 mA, IR = 100 mA 105 ns
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
LM5107 20130018.gif Figure 1. Timing Diagram

6.7 Typical Performance Characteristics

LM5107 20130004.gif
Figure 2. VDD Operating Current vs Frequency
LM5107 20130006.gif
Figure 4. Operating Current vs Temperature
LM5107 20130008.gif
Figure 6. Quiescent Current vs Voltage
LM5107 20130010.gif
Figure 8. LO and HO High Level Output Voltage vs Temperature
LM5107 20130012.gif
Figure 10. HO and LO Peak Output Current vs Output Voltage
LM5107 20130014.gif
Figure 12. Undervoltage Rising Thresholds vs Temperature
LM5107 20130016.gif
Figure 14. Input Thresholds vs Temperature
LM5107 20130005.gif
Figure 3. HB Operating Current vs Frequency
LM5107 20130007.gif
Figure 5. Quiescent Current vs Temperature
LM5107 20130009.gif
Figure 7. Propagation Delay vs Temperature
LM5107 20130011.gif
Figure 9. LO and HO Low Level Output Voltage vs Temperature
LM5107 20130013.gif
Figure 11. Doide Forward Voltage
LM5107 20130015.gif
Figure 13. Undervoltage Hysteresis vs Temperature
LM5107 20130017.gif
Figure 15. Input Thresholds vs Supply Voltage

7 Detailed Description

7.1 Overview

The LM5107 is designed to drive both the high-side and the low-side N-channel FETs in a synchronous buck or a half-bridge configuration. The outputs are independently controlled with TTL input thresholds. The floating high-side driver is capable of working with supply voltages up to 100 V. An integrated high voltage diode is provided to charge high side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high side gate driver. Undervoltage lockout is provided on both the low side and the high side power rails.

7.2 Functional Block Diagram

LM5107 20130001.gif

7.3 Feature Description

7.3.1 Start-up and UVLO

Both high and low-side drivers include under voltage lockout (UVLO) protection circuitry which monitors the supply voltage (VDD) and bootstrap capacitor voltage (VHB–HS) independently. The UVLO circuit inhibits each driver until sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to the VDD pin of the LM5107, the outputs of the low-side and high-side are held low until VDD exceeds the UVLO threshold, typically about 6.9 V. Any UVLO condition on the bootstrap capacitor will disable only the high-side output (HO).

7.3.2 Level Shift

The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides excellent delay matching with the low-side driver.

7.3.3 Bootstrap Diode

The bootstrap diode necessary to generate the high-side bias is included in the LM5107. The diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and reliable operation.

7.3.4 Output Stages

The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance, and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low-side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS.

7.4 Device Functional Modes

The device operates in normal mode and UVLO mode. See Start-up and UVLO for more information on UVLO operation mode. In normal mode, the output stage is dependent on the states of the HI and LI pins.

Table 1. Input/Output Logic Table

HI LI HO(1) LO(2)
L L L L
L H L H
H L H L
H H H H
(1) HO is measured with respect to the HS.
(2) LO is measured with the respect to the VSS.

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

To affect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching devices. With the advent of digital power, this situation will be often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver physically close to the power switch, driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses from the controller into the driver.

The LM5107 is a high voltage gate driver that is designed to drive both the high-side and low-side N-Channel MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck circuit. The floating high side driver is capable of operating with supply voltages up to 100 V. This allows for N-Channel MOSFET control in half-bridge, full-bridge, push-pull, two switch forward and active clamp topologies. The outputs are independently controlled. Each channel is controlled by its respective input pins (HI and LI), allowing full and independent flexibility to control on and off state of the output.

8.2 Typical Application

LM5107 typ_app_Rboot_snvs333.gif Figure 16. LM5107 Driving MOSFETs in Half-Bridge Configuration

8.2.1 Design Requirements

See Table 2 for the parameter and values.

Table 2. Operating Parameters

PARAMETER VALUE
Gate Driver LM5107
MOSFET CSD18531Q5A
VDD 10 V
Qgmax 43 nC
Fsw 100 kHz
Dmax 95%
IHBS 10 µA
VDH 1.0 V
VHBR 7.1 V
VHBH 0.4 V

8.2.2 Detailed Design Procedure

8.2.2.1 Select Bootstrap and VDD capacitor

The bootstrap capacitor must maintain the HB pin voltage above the UVLO voltage for the HB circuit in any circumstances during normal operation. Calculate the maximum allowable drop across the bootstrap capacitor with Equation 1.

Equation 1. ΔVHB = VDD – VDH – VHBL= 10 V – 1.0 V – 6.7 V = 2.3 V

where

  • VDD = Supply voltage of the gate drive IC
  • VDH = Bootstrap diode forward voltage drop
  • VHBL = VHBR – VHBH = 6.7 V, HB falling threshold

The quiescent current of the bootstrap circuit is 10 µA, which is negligible compared to the Qgs of the MOSFET
(see Equation 2 and Equation 3).

Equation 2. LM5107 equation_01_snosaw2.gif
Equation 3. LM5107 equation_02_snosaw2.gif

In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where the power stage may skip pulse due to load transients. It is recommended to place the bootstrap capacitor as close to the HB and HS pins as possible.

Equation 4. CBOOT = 100 nF

As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBOOT.

Equation 5. CVDD = 10 × CBOOT = 1 µF

The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be twice that of the maximum VDD to allow for loss of capacitance once the devices have a DC bias voltage across them and to ensure long-term reliability of the devices.

8.2.2.2 Select External Bootstrap Diode and Resistor

The bootstrap capacitor is charged by the VDD through the internal bootstrap diode every cycle when low side MOSFET turns on. The charging of the capacitor involves high peak currents, and therefore transient power dissipation in the internal bootstrap diode may be significant and dependent on its forward voltage drop. Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver and need to be considered in the gate driver IC power dissipation.

For high frequency and high capacitive loads, it may be necessary to consider using an external bootstrap diode placed in parallel with internal bootstrap diode to reduce power dissipation of the driver.

Bootstrap resistor RBOOT is selected to reduce the inrush current in DBOOT and limit the ramp up slew rate of voltage of HB-HS. It is recommended that RBOOT is between 2 Ω and 10 Ω. For this design, a current limiting resistor of 2.2 Ω is selected to limit inrush current of bootstrap diode.

Equation 6. LM5107 equation_03_snosaw2.gif

8.2.2.3 Select Gate Driver Resistor

Resistor RGATE is sized to reduce ringing caused by parasitic inductances and capacitances and also to limit the current coming out of the gate driver. For this design 7.5-Ω resistors were selected for this design. Maximum HO and LO drive current are calculated by Equation 7 through Equation 10.

Equation 7. LM5107 eq_07_snvs333.gif
Equation 8. LM5107 eq_08_snvs333.gif
Equation 9. LM5107 eq_09_snvs333.gif
Equation 10. LM5107 eq_10_snvs333.gif

where

  • IHOH = Maximum HO source current
  • ILOH = Maximum LO source current
  • IHOL = Maximum HO sink current
  • ILOH = Maximum HO sink current
  • VOH = High-Level output voltage drop across HB to HO or VDD to LO
  • VOL = Low-Level output voltage drop across HO to HS or LO to GND

8.2.3 Power Dissipation

Power dissipation of the gate driver has two portions as shown in Equation 11.

Equation 11. PDISS = PDC + PSW

Use Equation 12 to calculate the DC portion of the power dissipation (PDC).

Equation 12. PDC = IQ × VDD

where

  • IQ is the quiescent current for the driver.

The quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference voltage, logic circuits, protections, and also any current associated with switching of internal devices when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-through, and so forth). The power dissipated in the gate-driver package during switching (PSW) depends on the following factors:

  • Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to input bias supply voltage VDD)
  • Switching frequency
  • Use of external gate resistors. When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias supply is fairly simple. The energy that must be transferred from the bias supply to charge the capacitor is given by Equation 13.
    • Equation 13. EG = ½CLOAD × VDD2

    where

    • CLOAD is load capacitor
    • VDD is bias voltage feeding the driver

There is an equal amount of energy dissipated when the capacitor is charged and when it is discharged. This leads to a total power loss given by Equation 14.

Equation 14. PG = CLOAD × VDD2 × fSW

where

  • fSW is the switching frequency

The switching load presented by a power MOSFET is converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when switching a capacitor which is calculated using the equation QG = CLOAD × VDD to provide Equation 15 for power.

Equation 15. PG = CLOAD × VDD2 × fSW = QG × VDD × fSW

This power PG is dissipated in the resistive elements of the circuit when the MOSFET is being turned on and off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the driver and MOSFET, this power is completely dissipated inside the driver package. With the use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor.

8.2.4 Application Curves

LM5107 ai_LIHI_LOHO_on_nvs333.png
Figure 17. LI/HI to LO/HO Turn On Propagation Delay
LM5107 ai_LIHI_LOHO_off_nvs333.png
Figure 18. LI/HI to LO/HO Turn Off Propagation Delay

 
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