LM5107 100V / 1.4-A Peak Half Bridge Gate Driver

1 Features

Drives Both a High Side and Low Side N-Channel MOSFET
High Peak Output Current (1.4-A Sink / 1.3-A Source)
Independent TTL Compatible Inputs
Integrated Bootstrap Diode
Bootstrap Supply Voltage to 118 V DC
Fast Propagation Times (27-ns Typical)
Drives 1000 pF Load With 15-ns Rise and Fall Times
Excellent Propagation Delay Matching (2-ns Typical)
Supply Rail Undervoltage Lockout
Low Power Consumption
Pin Compatible With ISL6700
Packages:
- SOIC
- WSON (4 mm x 4 mm)

2 Applications

Current Fed Push-Pull Converters
Half and Full Bridge Power Converters
Solid State Motor Drives
Two Switch Forward Power Converters

3 Description

The LM5107 is a low cost high voltage gate driver, designed to drive both the high side and the low side N-Channel MOSFETs in a synchronous buck or a half bridge configuration. The floating high-side driver is capable of working with rail voltages up to 100-V. The outputs are independently controlled with TTL compatible input thresholds. An integrated on chip high voltage diode is provided to charge the high side gate drive bootstrap capacitor. A robust level shifter technology operates at high speed while consuming low power and providing clean level transitions from the control input logic to the high side gate driver. Undervoltage lockout is provided on both the low side and the high side power rails. The device is available in the SOIC and the thermally enhanced WSON packages.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LM5107	SOIC (8)	4.90 mm × 3.91 mm
LM5107	WSON (8)	4.00 mm × 4.00 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Block Diagram

4 Revision History

Changes from E Revision (March 2016) to F Revision

Changed Thermal Information tableGo
Added Overview and Device Functional Modes in Detailed Description sectionGo
Deleted HS Transient Voltages Below Ground from Application Information sectionGo
Added Typical Application section. Go
Added Power Supply Recommendations section. Go
Added Receiving Notification of Documentation Updates sectionGo

Changes from D Revision (March 2013) to E Revision

Added Device Information table, ESD Ratings, Pin Configuration and Functions section, Detailed Description section, Application and Implementation section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go

Changes from C Revision (March 2013) to D Revision

Changed layout of National Semiconductor Data Sheet to TI formatGo

5 Pin Configuration and Functions

D and NGT Packages

8-Pin SOIC, WSON

Top View

Pin Functions

PIN			DESCRIPTIONunder	APPLICATION INFORMATION
NO.		NAME
SOIC	WSON⁽¹⁾	NAME
1	1	V_DD	Positive gate drive supply	Locally decouple to V_SS using low ESR/ESL capacitor located as close to IC as possible.
2	2	HI	High side control input	The LM5107 HI input is compatible with TTL input thresholds. Unused HI input should be tied to ground and not left open
3	3	LI	Low side control input	The LM5107 LI input is compatible with TTL input thresholds. Unused LI input should be tied to ground and not left open.
4	4	V_SS	Ground reference	All signals are referenced to this ground.
5	5	LO	Low side gate driver output	Connect to the gate of the low side N-MOS device.
6	6	HS	High side source connection	Connect to the negative terminal of the bootstrap capacitor and to the source of the high side N-MOS device.
7	7	HO	High side gate driver output	Connect to the gate of the low side N-MOS device.
8	8	HB	High side gate driver positive supply rail	Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal of the bootstrap capacitor to HS. The bootstrap capacitor should be placed as close to IC as possible.

(1) For WSON package it is recommended that the exposed pad on the bottom of the LM5107 be soldered to ground plane on the PCB board and the ground plane should extend out from underneath the package to improve heat dissipation.

6 Specifications

6.1 Absolute Maximum Ratings

See ⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
	V_DD to V_SS	-0.3	18	V
	HB to HS	-0.3	18	V
	LI or HI to V_SS	-0.3	V_DD +0.3	V
	LO to V_SS	-0.3	V_DD +0.3	V
	HO to V_SS	V_HS − 0.3	V_HB + 0.3	V
	HS to V_SS⁽³⁾	−5	100	V
	HB to V_SS		118	V
T_J	Junction Temperature	-40	150	°C
T_stg	Storage Temperature Range	−55	150	°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test conditions, see the Electrical Characteristics.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than V_DD - 15V. For example, if V_DD = 10V, the negative transients at HS must not exceed -5V.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM)⁽¹⁾	±2000	V

(1) The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Pin 6 , Pin 7 and Pin 8 are rated at 500V.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
V_DD	8	14	V
HS⁽¹⁾	−1	V to 100	V
HB	V_HS + 8	V_HS + 14	V
HS Slew Rate	< 50		V/ns
Junction Temperature	−40	125	°C

(1) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than V_DD - 15V. For example, if V_DD = 10V, the negative transients at HS must not exceed -5V.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM5107		UNIT
		D (SOIC)	NGT (WSON)
		8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance ⁽²⁾	109.6	38.9⁽³⁾	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	51.7	37.5	°C/W
R_θJB	Junction-to-board thermal resistance	50.4	15.9	°C/W
ψ_JT	Junction-to-top characterization parameter	8.1	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	49.8	16.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	5	°C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application report.

(2) The θ_JA is not a constant for the package and depends on the printed circuit board design and the operating conditions.

(3) 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power planes embedded in PCB. See AN-1187 Leadless Leadframe Package (LLP) (SNOA401).

6.5 Electrical Characteristics

Unless otherwise specified, V_DD = V_HB = 12V, V_SS = V_HS = 0V, No Load on LO or HO. Typical limits are for T_J = +25°C, and minimum and maximum limits apply over the operating junction temperature range (–40°C to +125°C).

PARAMETER		TEST CONDITIONS	MIN⁽¹⁾	TYP	MAX⁽¹⁾	UNIT
SUPPLY CURRENTS
I_DD	V_DD Quiescent Current	LI = HI = 0V		0.3	0.6	mA
I_DDO	V_DD Operating Current	f = 500 kHz		2.1	3.4	mA
I_HB	Total HB Quiescent Current	LI = HI = 0V		0.06	0.2	mA
I_HBO	Total HB Operating Current	f = 500 kHz		1.6	3	mA
I_HBS	HB to V_SS Current, Quiescent	V_HS = V_HB = 100V		0.1	10	µA
I_HBSO	HB to V_SS Current, Operating	f = 500 kHz		0.5		mA
INPUT PINS LI and HI
V_IL	Low Level Input Voltage Threshold		0.8	1.8		V
V_IH	High Level Input Voltage Threshold			1.8	2.2	V
R_I	Input Pulldown Resistance		100	180	500	kΩ
UNDER VOLTAGE PROTECTION
V_DDR	V_DD Rising Threshold	V_DDR = V_DD - V_SS	6	6.9	7.4	V
V_DDH	V_DD Threshold Hysteresis			0.5		V
V_HBR	HB Rising Threshold	V_HBR = V_HB - V_HS	5.7	6.6	7.1	V
V_HBH	HB Threshold Hysteresis			0.4		V
BOOT STRAP DIODE
V_DL	Low-Current Forward Voltage	I_VDD-HB = 100 µA V_DL = V_DD - V_HB		0.58	0.9	V
V_DH	High-Current Forward Voltage	I_VDD-HB = 100 mA V_DH = V_DD - V_HB		0.82	1.1	V
R_D	Dynamic Resistance	I_VDD-HB = 100 mA		0.8	1.5	Ω
LO GATE DRIVER
V_OLL	Low-Level Output Voltage	I_LO = 100 mA V_OHL = V_LO – V_SS		0.28	0.45	V
V_OHL	High-Level Output Voltage	I_LO = −100 mA, V_OHL = V_DD– V_LO		0.45	0.75	V
I_OHL	Peak Pullup Current	V_LO = 0V		1.3		A
I_OLL	Peak Pulldown Current	V_LO = 12V		1.4		A
HO GATE DRIVER
V_OLH	Low-Level Output Voltage	I_HO = 100 mA V_OL_H = V_HO– V_HS		0.28	0.45	V
V_OHH	High-Level Output Voltage	I_HO = −100 mA V_OHH = V_HB– V_HO		0.45	0.75	V
I_OHH	Peak Pullup Current	V_HO = 0V		1.3		A
I_OLH	Peak Pulldown Current	V_HO = 12V		1.4		A

(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

6.6 Switching Characteristics

Parameter		CONDITIONS	TYP	MAX⁽¹⁾	UNIT
t_LPHL	Lower Turn-Off Propagation Delay (LI Falling to LO Falling)		27	56	ns
t_HPHL	Upper Turn-Off Propagation Delay (HI Falling to HO Falling)		27	56	ns
t_LPLH	Lower Turn-On Propagation Delay (LI Rising to LO Rising)		29	56	ns
t_HPLH	Upper Turn-On Propagation Delay (HI Rising to HO Rising)		29	56	ns
t_MON	Delay Matching: Lower Turn-On and Upper Turn-Off		2	15	ns
t_MOFF	Delay Matching: Lower Turn-Off and Upper Turn-On		2	15	ns
t_RC, t_FC	Either Output Rise/Fall Time	C_L = 1000 pF	15	–	ns
t_PW	Minimum Input Pulse Width that Changes the Output		50		ns
t_BS	Bootstrap Diode Turn-Off Time	I_F = 100 mA, I_R = 100 mA	105		ns