The LM5107 is a low cost high voltage gate driver, designed to drive both the high side and the low side N-Channel MOSFETs in a synchronous buck or a half bridge configuration. The floating high-side driver is capable of working with rail voltages up to 100-V. The outputs are independently controlled with TTL compatible input thresholds. An integrated on chip high voltage diode is provided to charge the high side gate drive bootstrap capacitor. A robust level shifter technology operates at high speed while consuming low power and providing clean level transitions from the control input logic to the high side gate driver. Undervoltage lockout is provided on both the low side and the high side power rails. The device is available in the SOIC and the thermally enhanced WSON packages.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LM5107 | SOIC (8) | 4.90 mm × 3.91 mm |
WSON (8) | 4.00 mm × 4.00 mm |
Changes from E Revision (March 2016) to F Revision
Changes from D Revision (March 2013) to E Revision
Changes from C Revision (March 2013) to D Revision
PIN | DESCRIPTIONunder | APPLICATION INFORMATION | ||
---|---|---|---|---|
NO. | NAME | |||
SOIC | WSON(1) | |||
1 | 1 | VDD | Positive gate drive supply | Locally decouple to VSS using low ESR/ESL capacitor located as close to IC as possible. |
2 | 2 | HI | High side control input | The LM5107 HI input is compatible with TTL input thresholds. Unused HI input should be tied to ground and not left open |
3 | 3 | LI | Low side control input | The LM5107 LI input is compatible with TTL input thresholds. Unused LI input should be tied to ground and not left open. |
4 | 4 | VSS | Ground reference | All signals are referenced to this ground. |
5 | 5 | LO | Low side gate driver output | Connect to the gate of the low side N-MOS device. |
6 | 6 | HS | High side source connection | Connect to the negative terminal of the bootstrap capacitor and to the source of the high side N-MOS device. |
7 | 7 | HO | High side gate driver output | Connect to the gate of the low side N-MOS device. |
8 | 8 | HB | High side gate driver positive supply rail | Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal of the bootstrap capacitor to HS. The bootstrap capacitor should be placed as close to IC as possible. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD to VSS | -0.3 | 18 | V | |
HB to HS | -0.3 | 18 | V | |
LI or HI to VSS | -0.3 | VDD +0.3 | V | |
LO to VSS | -0.3 | VDD +0.3 | V | |
HO to VSS | VHS − 0.3 | VHB + 0.3 | V | |
HS to VSS(3) | −5 | 100 | V | |
HB to VSS | 118 | V | ||
TJ | Junction Temperature | -40 | 150 | °C |
Tstg | Storage Temperature Range | −55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM)(1) | ±2000 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDD | 8 | 14 | V | ||
HS(1) | −1 | V to 100 | V | ||
HB | VHS + 8 | VHS + 14 | V | ||
HS Slew Rate | < 50 | V/ns | |||
Junction Temperature | −40 | 125 | °C |
THERMAL METRIC(1) | LM5107 | UNIT | ||
---|---|---|---|---|
D (SOIC) | NGT (WSON) | |||
8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance (2) | 109.6 | 38.9(3) | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 51.7 | 37.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 50.4 | 15.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 8.1 | 0.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 49.8 | 16.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | 5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN(1) | TYP | MAX(1) | UNIT | |
---|---|---|---|---|---|---|
SUPPLY CURRENTS | ||||||
IDD | VDD Quiescent Current | LI = HI = 0V | 0.3 | 0.6 | mA | |
IDDO | VDD Operating Current | f = 500 kHz | 2.1 | 3.4 | mA | |
IHB | Total HB Quiescent Current | LI = HI = 0V | 0.06 | 0.2 | mA | |
IHBO | Total HB Operating Current | f = 500 kHz | 1.6 | 3 | mA | |
IHBS | HB to VSS Current, Quiescent | VHS = VHB = 100V | 0.1 | 10 | µA | |
IHBSO | HB to VSS Current, Operating | f = 500 kHz | 0.5 | mA | ||
INPUT PINS LI and HI | ||||||
VIL | Low Level Input Voltage Threshold | 0.8 | 1.8 | V | ||
VIH | High Level Input Voltage Threshold | 1.8 | 2.2 | V | ||
RI | Input Pulldown Resistance | 100 | 180 | 500 | kΩ | |
UNDER VOLTAGE PROTECTION | ||||||
VDDR | VDD Rising Threshold | VDDR = VDD - VSS | 6 | 6.9 | 7.4 | V |
VDDH | VDD Threshold Hysteresis | 0.5 | V | |||
VHBR | HB Rising Threshold | VHBR = VHB - VHS | 5.7 | 6.6 | 7.1 | V |
VHBH | HB Threshold Hysteresis | 0.4 | V | |||
BOOT STRAP DIODE | ||||||
VDL | Low-Current Forward Voltage | IVDD-HB = 100 µA VDL = VDD - VHB |
0.58 | 0.9 | V | |
VDH | High-Current Forward Voltage | IVDD-HB = 100 mA VDH = VDD - VHB |
0.82 | 1.1 | V | |
RD | Dynamic Resistance | IVDD-HB = 100 mA | 0.8 | 1.5 | Ω | |
LO GATE DRIVER | ||||||
VOLL | Low-Level Output Voltage | ILO = 100 mA VOHL = VLO – VSS |
0.28 | 0.45 | V | |
VOHL | High-Level Output Voltage | ILO = −100 mA, VOHL = VDD– VLO |
0.45 | 0.75 | V | |
IOHL | Peak Pullup Current | VLO = 0V | 1.3 | A | ||
IOLL | Peak Pulldown Current | VLO = 12V | 1.4 | A | ||
HO GATE DRIVER | ||||||
VOLH | Low-Level Output Voltage | IHO = 100 mA VOLH = VHO– VHS |
0.28 | 0.45 | V | |
VOHH | High-Level Output Voltage | IHO = −100 mA VOHH = VHB– VHO |
0.45 | 0.75 | V | |
IOHH | Peak Pullup Current | VHO = 0V | 1.3 | A | ||
IOLH | Peak Pulldown Current | VHO = 12V | 1.4 | A |
Parameter | CONDITIONS | MIN(1) | TYP | MAX(1) | UNIT | |
---|---|---|---|---|---|---|
tLPHL | Lower Turn-Off Propagation Delay (LI Falling to LO Falling) |
27 | 56 | ns | ||
tHPHL | Upper Turn-Off Propagation Delay (HI Falling to HO Falling) |
27 | 56 | ns | ||
tLPLH | Lower Turn-On Propagation Delay (LI Rising to LO Rising) |
29 | 56 | ns | ||
tHPLH | Upper Turn-On Propagation Delay (HI Rising to HO Rising) |
29 | 56 | ns | ||
tMON | Delay Matching: Lower Turn-On and Upper Turn-Off | 2 | 15 | ns | ||
tMOFF | Delay Matching: Lower Turn-Off and Upper Turn-On | 2 | 15 | ns | ||
tRC, tFC | Either Output Rise/Fall Time | CL = 1000 pF | 15 | – | ns | |
tPW | Minimum Input Pulse Width that Changes the Output | 50 | ns | |||
tBS | Bootstrap Diode Turn-Off Time | IF = 100 mA, IR = 100 mA | 105 | ns |
The LM5107 is designed to drive both the high-side and the low-side N-channel FETs in a synchronous buck or a half-bridge configuration. The outputs are independently controlled with TTL input thresholds. The floating high-side driver is capable of working with supply voltages up to 100 V. An integrated high voltage diode is provided to charge high side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high side gate driver. Undervoltage lockout is provided on both the low side and the high side power rails.
Both high and low-side drivers include under voltage lockout (UVLO) protection circuitry which monitors the supply voltage (VDD) and bootstrap capacitor voltage (VHB–HS) independently. The UVLO circuit inhibits each driver until sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to the VDD pin of the LM5107, the outputs of the low-side and high-side are held low until VDD exceeds the UVLO threshold, typically about 6.9 V. Any UVLO condition on the bootstrap capacitor will disable only the high-side output (HO).
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides excellent delay matching with the low-side driver.
The bootstrap diode necessary to generate the high-side bias is included in the LM5107. The diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and reliable operation.
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance, and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low-side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS.
The device operates in normal mode and UVLO mode. See Start-up and UVLO for more information on UVLO operation mode. In normal mode, the output stage is dependent on the states of the HI and LI pins.