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  • LM5109A High Voltage 1A Peak Half Bridge Gate Driver

    • SNVS412C April   2006  – September 2016 LM5109A

      PRODUCTION DATA.  

  • CONTENTS
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  • LM5109A High Voltage 1A Peak Half Bridge Gate Driver
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start-Up and UVLO
      2. 7.3.2 Level Shift
      3. 7.3.3 Output Stages
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 HS Transient Voltages Below Ground
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD Capacitor
        2. 8.2.2.2 Select External Bootstrap Diode and Its Series Resistor
        3. 8.2.2.3 Selecting External Gate Driver Resistor
        4. 8.2.2.4 Estimate the Driver Power Loss
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • D|8
    • MSOI002K
  • NGT|8
    • MPDS406A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • snvs412c_oa
  • snvs412c_pm
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DATA SHEET

LM5109A High Voltage 1A Peak Half Bridge Gate Driver

1 Features

  • Drives Both a High-Side and Low-Side N-Channel MOSFET
  • 1A peak Output Current (1.0A Sink / 1.0A Source)
  • Independent TTL Compatible Inputs
  • Bootstrap Supply Voltage to 108V DC
  • Fast Propagation Times (30 ns Typical)
  • Drives 1000 pF Load with 15ns Rise and Fall Times
  • Excellent Propagation Delay Matching (2 ns Typical)
  • Supply Rail Under-Voltage Lockout
  • Low Power Consumption
  • Pin Compatible with ISL6700
  • Industry Standard SOIC-8 and Thermally Enhanced WSON-8 Package

2 Applications

  • Current Fed Push-Pull Converters
  • Half and Full Bridge Power Converters
  • Solid State Motor Drives
  • Two Switch Forward Power Converters

3 Description

The LM5109A is a cost effective, high voltage gate driver designed to drive both the high-side and the low-side N-Channel MOSFETs in a synchronous buck or a half bridge configuration. The floating high-side driver is capable of working with rail voltages up to 90V. The outputs are independently controlled with TTL compatible input thresholds. The robust level shift technology operates at high speed while consuming low power and providing clean level transitions from the control input logic to the high-side gate driver. Under-voltage lockout is provided on both the low-side and the high-side power rails. The device is available in the SOIC and the thermally enhanced WSON packages.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LM5109A SOIC (8) 4.90 mm × 3.91 mm
WSON (8) 4.00 mm × 4.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Application Diagram

LM5109A simplified_application_snvsag6.gif

4 Revision History

Changes from B Revision (March 2016) to C Revision

  • Updated values in the Thermal Information table to align with JEDEC standards.Go
  • Added Overview section.Go
  • Added Feature Description section.Go
  • Added Device Functional Modes section.Go
  • Added Typical Application section.Go
  • Added Power Supply Recommendations section. Go

Changes from A Revision (March 2013) to B Revision

  • Added Device Information table, ESD Ratings, Pin Configuration and Functions section, Detailed Description section, Application and Implementation section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go

Changes from * Revision (March 2013) to A Revision

  • Changed layout of National Semiconductor Data Sheet to TI formatGo

5 Pin Configuration and Functions

D Package
8-Pin SOIC
Top View
LM5109A 20170202.gif
NGT Package
8-Pin WSON
Top View
LM5109A 20170203.gif

Pin Functions

Pin # NAME DESCRIPTION APPLICATION INFORMATION
SOIC WSON(1)
1 1 VDD Positive gate drive supply Locally decouple to VSS using low ESR/ESL capacitor located as close to IC as possible.
2 2 HI High side control input The HI input is compatible with TTL input thresholds. Unused HI input should be tied to ground and not left open
3 3 LI Low side control input The LI input is compatible with TTL input thresholds. Unused LI input should be tied to ground and not left open.
4 4 VSS Ground reference All signals are referenced to this ground.
5 5 LO Low side gate driver output Connect to the gate of the low-side N- MOS device.
6 6 HS High side source connection Connect to the negative terminal of the bootstrap capacitor and to the source of the high-side N-MOS device.
7 7 HO High side gate driver output Connect to the gate of the high-side N-MOS device.
8 8 HB High side gate driver positive supply rail Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal of the bootstrap capacitor to HS. The bootstrap capacitor should be placed as close to IC as possible.
(1) For WSON package it is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PCB and the ground plane should extend out from underneath the package to improve heat dissipation.

6 Specifications

6.1 Absolute Maximum Ratings

See (1)(2)
MIN MAX UNIT
VDD to VSS –0.3 18 V
HB to HS −0.3 18 V
LI or HI to VSS −0.3 VDD + 0.3 V
LO to VSS −0.3 VDD + 0.3 V
HO to VSS VHS − 0.3 VHB + 0.3 V
HS to VSS(3) −5 90 V
HB to VSS 108 V
Junction Temperature –40 150 °C
Storage Temperature Range −55 150 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed –1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15V. For example, if VDD = 10V, the negative transients at HS must not exceed –5V.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM) (1) ±1500 V
(1) The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD 8 14 V
HS(1) −1 90 V
HB VHS + 8 VHS + 14 V
HS Slew Rate < 50 V/ns
Junction Temperature −40 125 °C
(1) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed –1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15V. For example, if VDD = 10V, the negative transients at HS must not exceed –5V.

6.4 Thermal Information

THERMAL METRIC(1) LM5109A UNIT
D (SOIC) NGT (WSON)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 117.6 42.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 64.9 34 °C/W
RθJB Junction-to-board thermal resistance 58.1 19.3 °C/W
ψJT Junction-to-top characterization parameter 17.4 0.4 °C/W
ψJB Junction-to-board characterization parameter 57.6 19.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance – 8.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO(1). Typical limits are for TJ = 25°C, and minimum and maximum limits apply over the operating junction temperature range (–40°C to 125°C).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IDD VDD quiescent current LI = HI = 0V 0.3 0.6 mA
IDDO VDD operating current f = 500 kHz 1.8 2.9 mA
IHB Total HB quiescent current LI = HI = 0V 0.06 0.2 mA
IHBO Total HB operating current f = 500 kHz 1.4 2.8 mA
IHBS HB to VSS current, quiescent VHS = VHB = 90V 0.1 10 µA
IHBSO HB to VSS current, operating f = 500 kHz 0.5 mA
INPUT PINS LI and HI
VIL Low-level input voltage threshold 0.8 1.8 V
VIH High-level input voltage threshold 1.8 2.2 V
RI Input pulldown resistance 100 200 500 kΩ
UNDER-VOLTAGE PROTECTION
VDDR VDD rising threshold VDDR = VDD – VSS 6.0 6.7 7.4 V
VDDH VDD threshold hysteresis 0.5 V
VHBR HB rising threshold VHBR = VHB – VHS 5.7 6.6 7.1 V
VHBH HB threshold hysteresis 0.4 V
LO GATE DRIVER
VOLL Low-level output voltage ILO = 100 mA, VOHL = VLO – VSS 0.38 0.65 V
VOHL High-level output voltage ILO = −100 mA, VOHL = VDD – VLO 0.72 1.20 V
IOHL Peak pullup current VLO = 0V 1.0 A
IOLL Peak pulldown current VLO = 12V 1.0 A
HO GATE DRIVER
VOLH Low-level output voltage IHO = 100 mA, VOLH = VHO – VHS 0.38 0.65 V
VOHH High-level output voltage IHO = −100 mA, VOHH = VHB – VHO 0.72 1.20 V
IOHH Peak pullup current VHO = 0V 1.0 A
IOLH Peak pulldown current VHO = 12V 1.0 A
(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

6.6 Switching Characteristics

Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO. Typical limits are for TJ = 25°C, and minimum and maximum limits apply over the operating junction temperature range (–40°C to 125°C).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tLPHL Lower turn-off propagation delay
(LI falling to LO falling)		 30 56 ns
tHPHL Upper turn-off propagation delay
(HI falling to HO falling)		 30 56 ns
tLPLH Lower turn-on propagation delay
(LI rising to LO rising)		 32 56 ns
tHPLH Upper turn-on propagation delay
(HI rising to HO rising)		 32 56 ns
tMON Delay matching: lower turn-on and upper turn-off 2 15 ns
tMOFF Delay matching: lower turn-off and upper turn-on 2 15 ns
tRC, tFC Either output rise or fall time CL = 1000 pF 15 - ns
tPW Minimum input pulse width that changes the output 50 ns
LM5109A 20170218.gif Figure 1. Timing Diagram

6.7 Typical Performance Characteristics

LM5109A 20170204.gif
Figure 2. VDD Operating Current vs Frequency
LM5109A 20170206.gif
Figure 4. Operating Current vs Temperature
LM5109A 20170208.gif
Figure 6. Quiescent Current vs Voltage
LM5109A 20170210.gif
Figure 8. LO and HO High Level Output Voltage vs Temperature
LM5109A 20170214.gif
Figure 10. Undervoltage Rising Thresholds vs Temperature
LM5109A 20170216.gif
Figure 12. Input Thresholds vs Temperature
LM5109A 20211905.gif
VDD = VHB = 12 V VSS = VHS = 0 V
Figure 3. HB Operating Current vs Frequency
LM5109A 20170207.gif
Figure 5. Quiescent Current vs Temperature
LM5109A 20170209.gif
Figure 7. Propagation Delay vs Temperature
LM5109A 20170211.gif
Figure 9. LO and HO Low Level Output Voltage vs Temperature
LM5109A 20170215.gif
Figure 11. Undervoltage Hysteresis vs Temperature
LM5109A 20170217.gif
Figure 13. Input Thresholds vs Supply Voltage

 
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