LM5109B-Q1 High Voltage 1-A Peak Half Bridge Gate Driver
- SNVSAG6A November 2015 – December 2015 LM5109B-Q1
  
  PRODUCTION DATA.

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DATA SHEET

LM5109B-Q1 High Voltage 1-A Peak Half Bridge Gate Driver

1 Features

Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results
- Device Temperature Grade 1
- Device HBM ESD Classification Level 1C
- Device CDM ESD Classification Level C4A
Drives Both a High-Side and Low-Side N-Channel MOSFET
1-A Peak Output Current (1.0-A Sink/1.0-A Source)
Independent TTL/CMOS Compatible Inputs
Bootstrap Supply Voltage to 108-V DC
Fast Propagation Times (30 ns Typical)
Drives 1000-pF Load with 15-ns Rise and Fall Times
Excellent Propagation Delay Matching (2 ns Typical)
Supply Rail Under-Voltage Lockout
Low Power Consumption
Thermally-Enhanced WSON-8 Package

2 Applications

Push-Pull Converters
Half and Full Bridge Power Converters
Solid State Motor Drives
Two Switch Forward Power Converters

3 Description

The LM5109B-Q1 is a cost effective, high voltage gate driver designed to drive both the high-side and the low-side N-Channel MOSFETs in a synchronous buck or a half bridge configuration. The floating high-side driver is capable of working with rail voltages up to 90 V. The outputs are independently controlled with TTL/CMOS compatible logic input thresholds. The robust level shift technology operates at high speed while consuming low power and providing clean level transitions from the control input logic to the high-side gate driver. Under-voltage lockout is provided on both the low-side and the high-side power rails. The device is available in the thermally enhanced WSON(8) packages.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LM5109B-Q1	WSON (8)	4.00 mm × 4.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Application Diagram

LM5109B-Q1 simplified_application_snvsag6.gif

4 Revision History

Changes from * Revision (November 2015) to A Revision

Changed device from Product Preview to Production Data and released full data sheetGo

Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
V_DD to V_SS	–0.3	18	V
HB to HS	–0.3	18	V
LI or HI to V_SS	–0.3	V_DD + 0.3	V
LO to V_SS	–0.3	V_DD+ 0.3	V
HO to V_SS	V_HS– 0.3	V_HB + 0.3	V
HS to V_SS⁽¹⁾	–5	90	V
HB to V_SS		108	V
Junction temperature	–40	150	°C
Storage temperature, T_stg	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

4.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	1500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	750	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
V_DD	8	14	V
HS⁽¹⁾	–1	90	V
HB	V_HS+8	V_HS+14	V
HS Slew Rate		< 50	V/ns
Junction Temperature	–40	125	°C

(1) In the application, the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than V_DD – 15 V. For example, if V_DD = 10 V, the negative transients at HS must not exceed –5 V.

4.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM5109B-Q1	UNIT
		NGT (WSON)
		8-PINS
R_θJA	Junction-to-ambient thermal resistance	42.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	34.0	°C/W
R_θJB	Junction-to-board thermal resistance	19.3	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	19.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	8.1	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

4.5 Electrical Characteristics

T_J = 25°C (unless otherwise noted)
V_DD = V_HB = 12 V, V_SS = V_HS = 0 V, No Load on LO or HO.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
Supply Currents
I_DD	V_DD Quiescent Current	LI = HI = 0V	T_J = 25°C		0.3		mA
I_DD	V_DD Quiescent Current	LI = HI = 0V	T_J = –40°C to 125°C			0.6	mA
I_DDO	V_DD Operating Current	f = 500 kHz	T_J = 25°C		1.8		mA
I_DDO	V_DD Operating Current	f = 500 kHz	T_J = –40°C to 125°C			2.9	mA
I_HB	Total HB Quiescent Current	LI = HI = 0V	T_J = 25°C		0.06		mA
I_HB	Total HB Quiescent Current	LI = HI = 0V	T_J = –40°C to 125°C			0.2	mA
I_HBO	Total HB Operating Current	f = 500 kHz	T_J = 25°C		1.4		mA
I_HBO	Total HB Operating Current	f = 500 kHz	T_J = –40°C to 125°C			2.8	mA
I_HBS	HB to V_SS Current, Quiescent	V_HS = V_HB = 90V	T_J = 25°C		0.1		µA
I_HBS	HB to V_SS Current, Quiescent	V_HS = V_HB = 90V	T_J = –40°C to 125°C			10	µA
I_HBSO	HB to V_SS Current, Operating	f = 500 kHz			0.5		mA
Input Pins Li and Hi
V_IL	Low Level Input Voltage Threshold	T_J = 25°C			1.8		V
V_IL	Low Level Input Voltage Threshold	T_J = –40°C to 125°C		0.8			V
V_IH	High Level Input Voltage Threshold	T_J = 25°C			1.8		V
V_IH	High Level Input Voltage Threshold	T_J = –40°C to 125°C				2.2	V
R_I	Input Pulldown Resistance	T_J = 25°C			200		kΩ
R_I	Input Pulldown Resistance	T_J = –40°C to 125°C		100		500	kΩ
Under Voltage Protection
V_DDR	V_DD Rising Threshold	V_DDR = V_DD - V_SS	T_J = 25°C		6.7		V
V_DDR	V_DD Rising Threshold	V_DDR = V_DD - V_SS	T_J = –40°C to 125°C	6.0		7.4	V
V_DDH	V_DD Threshold Hysteresis				0.5		V
V_HBR	HB Rising Threshold	V_HBR = V_HB - V_HS	T_J = 25°C		6.6		V
V_HBR	HB Rising Threshold	V_HBR = V_HB - V_HS	T_J = –40°C to 125°C	5.7		7.1	V
V_HBH	HB Threshold Hysteresis				0.4		V
LO Gate Driver
V_OLL	Low-Level Output Voltage	I_LO = 100 mA, V_OHL = V_LO – V_SS	T_J = 25°C		0.38		V
V_OLL	Low-Level Output Voltage	I_LO = 100 mA, V_OHL = V_LO – V_SS	T_J = –40°C to 125°C			0.65	V
V_OHL	High-Level Output Voltage	I_LO = −100 mA, V_OHL = V_DD– V_LO	T_J = 25°C		0.72		V
V_OHL	High-Level Output Voltage	I_LO = −100 mA, V_OHL = V_DD– V_LO	T_J = –40°C to 125°C			1.20	V
I_OHL	Peak Pullup Current	V_LO = 0V			1.0		A
I_OLL	Peak Pulldown Current	V_LO = 12V			1.0		A
HO Gate Driver
V_OLH	Low-Level Output Voltage	I_HO = 100 mA, V_OL_H = V_HO– V_HS	T_J = 25°C		0.38		V
V_OLH	Low-Level Output Voltage	I_HO = 100 mA, V_OL_H = V_HO– V_HS	T_J = –40°C to 125°C			0.65	V
V_OHH	High-Level Output Voltage	I_HO = −100 mA, V_OHH = V_HB– V_HO	T_J = 25°C		0.72		V
V_OHH	High-Level Output Voltage	I_HO = −100 mA, V_OHH = V_HB– V_HO	T_J = –40°C to 125°C			1.20	V
I_OHH	Peak Pullup Current	V_HO = 0V			1.0		A
I_OLH	Peak Pulldown Current	V_HO = 12V			1.0		A

4.6 Switching Characteristics

T_J = 25°C (unless otherwise noted)
V_DD = V_HB = 12 V, V_SS = V_HS = 0 V, No Load on LO or HO.

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
t_LPHL	Lower Turn-Off Propagation Delay (LI Falling to LO Falling)	T_J = 25°C	30		ns
t_LPHL	Lower Turn-Off Propagation Delay (LI Falling to LO Falling)	T_J = –40°C to 125°C		56	ns
t_HPHL	Upper Turn-Off Propagation Delay (HI Falling to HO Falling)	T_J = 25°C	30		ns
t_HPHL	Upper Turn-Off Propagation Delay (HI Falling to HO Falling)	T_J = –40°C to 125°C		56	ns
t_LPLH	Lower Turn-On Propagation Delay (LI Rising to LO Rising)	T_J = 25°C	32		ns
t_LPLH	Lower Turn-On Propagation Delay (LI Rising to LO Rising)	T_J = –40°C to 125°C		56	ns
t_HPLH	Upper Turn-On Propagation Delay (HI Rising to HO Rising)	T_J = 25°C	32		ns
t_HPLH	Upper Turn-On Propagation Delay (HI Rising to HO Rising)	T_J = –40°C to 125°C		56	ns
t_MON	Delay Matching: Lower Turn-On and Upper Turn-Off	T_J = 25°C	2		ns
t_MON	Delay Matching: Lower Turn-On and Upper Turn-Off	T_J = –40°C to 125°C		15	ns
t_MOFF	Delay Matching: Lower Turn-Off and Upper Turn-On	T_J = 25°C	2		ns
t_MOFF	Delay Matching: Lower Turn-Off and Upper Turn-On	T_J = –40°C to 125°C		15	ns
t_RC, t_FC	Either Output Rise/Fall Time	C_L = 1000 pF	15		ns
t_PW	Minimum Input Pulse Width that Changes the Output		50		ns

Figure 1. Typical Test Timing Diagram

4.7 Typical Characteristics

Figure 2. V_DD Operating Current vs Frequency

Figure 4. Operating Current vs Temperature

Figure 6. Quiescent Current vs Voltage

Figure 8. LO and HO High Level Output Voltage vs Temperature

Figure 10. Undervoltage Rising Thresholds vs Temperature

Figure 12. Input Thresholds vs Temperature

V_DD = V_HB = 12 V

V_SS = V_HS = 0 V

Figure 3. HB Operating Current vs Frequency

Figure 5. Quiescent Current vs Temperature

Figure 7. Propagation Delay vs Temperature

Figure 9. LO and HO Low Level Output Voltage vs Temperature

Figure 11. Undervoltage Hysteresis vs Temperature

Figure 13. Input Thresholds vs Supply Voltage

5 Detailed Description

5.1 Overview

The LM5109B-Q1 is a cost-effective, high voltage gate driver designed to drive both the high-side and the low-side N-channel FETs in a synchronous buck or a half-bridge configuration. The outputs are independently controlled with TTL/CMOS compatible input thresholds. The floating high-side driver is capable of working with HB voltage up to 108 V. An external high voltage diode must be provided to charge high side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high side gate driver. Under-voltage lockout (UVLO) is provided on both the low side and the high side power rails.

5.2 Functional Block Diagram

5.3 Feature Description

5.3.1 Start-up and UVLO

Both top and bottom drivers include UVLO protection circuitry which monitors the supply voltage (V_DD) and bootstrap capacitor voltage (V_HB–HS) independently. The UVLO circuit inhibits each output until sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO hysteresis prevents chattering during supply voltage variations. When the supply voltage is applied to the VDD pin of the LM5109B-Q1, the top and bottom gates are held low until V_DD exceeds the UVLO threshold, typically about 6.7 V. Any UVLO condition on the bootstrap capacitor (V_HB–HS) will only disable the high- side output (HO).

Table 1. VDD UVLO Feature Logic Operation

Condition (V_HB-HS>V_HBR for all case below)	HI	LI	HO	LO
V_DD-V_SS < V_DDR during device start-up	H	L	L	L
V_DD-V_SS < V_DDR during device start-up	L	H	L	L
V_DD-V_SS < V_DDR during device start-up	H	H	L	L
V_DD-V_SS < V_DDR during device start-up	L	L	L	L
V_DD-V_SS < V_DDR – V_DDH after device start-up	H	L	L	L
V_DD-V_SS < V_DDR – V_DDH after device start-up	L	H	L	L
V_DD-V_SS < V_DDR – V_DDH after device start-up	H	H	L	L
V_DD-V_SS < V_DDR – V_DDH after device start-up	L	L	L	L

Table 2. VHB-HS UVLO Feature Logic Operation

Condition (V_DD>V_DDR for all case below)	HI	LI	HO	LO
V_HB-HS < V_HBR during device start-up	H	L	L	L
V_HB-HS < V_HBR during device start-up	L	H	L	H
V_HB-HS < V_HBR during device start-up	H	H	L	H
V_HB-HS < V_HBR during device start-up	L	L	L	L
V_HB-HS < V_HBR – V_HBH after device start-up	H	L	L	L
V_HB-HS < V_HBR – V_HBH after device start-up	L	H	L	H
V_HB-HS < V_HBR – V_HBH after device start-up	H	H	L	H
V_HB-HS < V_HBR – V_HBH after device start-up	L	L	L	L

5.3.2 Level Shift

The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output which is referenced to the HS pin and provides excellent delay matching with the low-side driver.

5.3.3 Output Stages

The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance, and high peak current capability of both outputs allow for efficient switching of the power MOSFETs. The low-side output stage is referenced to VSS and the high-side is referenced to HS.

5.4 HS Transient Voltages Below Ground

The HS node will always be clamped by the body diode of the lower external FET. In some situations, board resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS node can swing below ground provided:

HS must always be at a lower potential than HO. Pulling HO more than –0.3 V below HS can activate parasitic transistors resulting in excessive current flow from the HB supply, possibly resulting in damage to the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must be placed as close to the IC pins as possible in order to be effective.
HB to HS operating voltage should be 15 V or less. Hence, if the HS pin transient voltage is –5 V, VDD should be ideally limited to 10 V to keep HB to HS below 15 V.
Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation. The capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO and HO can be quite large. Any series inductances with the bypass capacitor will cause voltage ringing at the leads of the IC which must be avoided for reliable operation.

5.5 Device Functional Modes

The device operates in normal mode and UVLO mode. See Start-up and UVLO for more information on UVLO operation mode. In normal mode when the V_DD and V_HB–HS are above UVLO threshold, the output stage is dependent on the states of the HI and LI pins. The output HO and LO will be low if input state is floating.

Table 3. INPUT/OUTPUT Logic Table

HI	LI	HO⁽¹⁾	LO⁽²⁾
L	L	L	L
L	H	L	H
H	L	H	L
H	H	H	H
Floating	Floating	L	L

(1) HO is measured with respect to the HS.

(2) LO is measured with respect to the VSS.