The LM5140-Q1 is a dual synchronous buck controller intended for high voltage wide VIN step-down converter applications. The control method is based on current mode control. Current mode control provides inherent line feedforward, cycle-by-cycle current limiting, and easier loop compensation.
The LM5140-Q1 features adjustable slew rate control to simplify compliance with the CISPR and automotive EMI requirements. The LM5140-Q1 operates at selectable switching frequencies of 2.2 MHz or 440 kHz with the two controller channels switching 180º out of phase. In light or no-load conditions, the LM5140-Q1 operates in skip cycle mode for improved low power efficiency. The LM5140-Q1 includes a high voltage bias regulator with automatic switchover to an external bias supply to improve efficiency and reduce input current. Additional features include frequency synchronization, cycle-by-cycle current limit, hiccup mode fault protection for sustained overloads, independent power good outputs, and independent enable inputs.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LM5140-Q1 | VQFN (40) | 6.00 mm × 6.00 mm |
Changes from * Revision (January 2016) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | SS2 | I | Channel 2 soft-start programming pin. An external capacitor and an internal 20-μA current source set the ramp rate of the internal error amplifier reference during soft-start. Pulling SS pin below 80 mV turns off the channel 2 gate driver outputs, but all the other functions remain active. |
2 | COMP2 | O | Output of the channel 2 transconductance error amplifier. |
3 | FB2 | I | Feedback input of channel 2. Connect the FB2 pin to VDD for a 5-V output or connect FB2 to ground for a fixed 8-V output. A resistive divider from the VOUT2 to the FB2 pin sets the output voltage level between 1.5 V and 15 V. The regulation threshold at the FB2 pin is 1.2 V. |
4 | CS2 | I | Channel 2 current sense amplifier input. Make a low current Kelvin connection between this pin and the inductor side of the external current sense resistor. |
5 | VOUT2 | I | Output and the current sense amplifier input of channel 2 . Connect this pin to the output side of the channel 2 current sense resistor. |
6 | VCCX | I | Optional input for an external bias supply. If VCCX > 4.5 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled. If VCCX is unused, it must be grounded. |
7 | PG2 | O | An open-collector output which goes low if VOUT2 is outside a specified regulation window. |
8 | HOL2 | O | Channel 2 high-side gate driver turnoff output. |
9 | HO2 | O | Channel 2 high-side gate driver turnon output. |
10 | SW2 | I | Switching node of the channel 2 buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET. |
11 | HB2 | O | Channel 2 high-side driver supply for bootstrap gate drive. |
12 | LOL2 | O | Channel 2 low-side gate driver turnoff output. |
13 | LO2 | O | Channel 2 low-side gate driver turnon output. |
14 | PGND2 | G | Power ground connection pin for low-side NMOS gate driver. |
15 | VCC | P | VCC bias supply pin. Pin 15 and pin 16 must to be connected together on the PCB. |
16 | VCC | P | VCC bias supply pin. Pin 15 and pin 16 must to be connected together on the PCB. |
17 | PGND1 | G | Power ground connection pin for low-side NMOS gate driver. |
18 | LO1 | O | Channel 1 low-side gate driver turnon output. |
19 | LOL1 | O | Channel 1 low-side gate driver turnoff output. |
20 | HB1 | O | Channel 1 high-side driver supply for bootstrap gate drive. |
21 | SW1 | I | Switching node of the channel 1 buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET. |
22 | HO1 | O | Channel 1 high-side gate driver turnon output |
23 | HOL1 | O | Channel 1 high-side gate driver turnoff output. |
24 | PG1 | O | An open-collector output which goes low if VOUT1 is outside a specified regulation window. |
25 | VIN | P | Supply voltage input source for the VCC regulators. |
26 | VOUT1 | I | VOUT1 and current sense amplifier input of channel 1. Connect to the output side of the channel 1 current sense resistor. |
27 | CS1 | I | Channel 1 current sense amplifier input. Make a low current Kelvin connection between this pin and the inductor side of the external current sense resistor. |
28 | FB1 | I | Feedback input of channel 1. Connect the FB1 pin to VDDA for a 3.3-V output or connect FB1 to ground for a 5-V output. A resistive divider from the VOUT1 to the FB1 pin sets the output voltage level between 1.5 V and 15 V. The regulation threshold at the FB1 pin is 1.2 V. |
29 | COMP1 | O | Output of the channel 1 transconductance error amplifier. |
30 | SS1 | I | Channel 2 soft-start programming pin. An external capacitor and an internal 20-μA current source set the ramp rate of the internal error amplifier reference during soft-start. Pulling SS pin below 80 mV turns off the channel 1 gate driver outputs, but the all the other function remain active. |
31 | EN1 | I | An active high logic input enables channel 1. |
32 | RES | O | Restart timer pin. An external capacitor configures the hiccup mode current limiting. The capacitor at the RES pin determines the time the controller remains off before automatically restarting in hiccup mode. The two regulator channels operate independently. One channel may operate in normal mode while the other is in hiccup mode overload protection. The hiccup mode commences when either channel experiences 512 consecutive PWM cycles with cycle-by-cycle current limiting. Connect the RES pin to VDD during power up to disable hiccup mode protection. |
33 | DEMB | I | Diode Emulation pin. If the DEMB pin is grounded, diode emulation is enabled. If it is connected to VDDA the LM5140-Q1 operates in FPWM mode with continuous conduction at light loads. |
34 | ILSET | I | Current Limit Threshold pin. Connecting the ILSET pin to VDDA sets the current limit threshold to 73 mV for channel 1 and channel 2. Connecting the ILSET pin to GND sets the current limit thresholds to 48 mV. |
35 | AGND | G | Analog ground connection. Ground return for the internal voltage reference and analog circuits. |
36 | VDDA | P | Internal analog bias regulator output. Connect a capacitor from the VDDA pin the AGND. |
37 | OSC | I | Frequency selection pin. Connecting the OSC pin to VDDA selects the default oscillator frequency of 2.2 MHz. Connecting the OSC pin to ground sets frequency to 440 kHz. |
38 | SYNIN | I | Sync input pin. The internal oscillator can be synchronized to an external clock. If the synchronization feature is not used, the SYNIN pin must be connected to AGND. |
39 | SYNOUT | O | Sync output pin. The TTL level output signal is 180º out of phase with the HO1 gate drive of channel 1. |
40 | EN2 | I | An active high logic input enables channel 2. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VIN | –0.3 | 70 | V |
SW1,SW2 to PGND | –0.3 | 70 | V | |
SW1, SW2 to PGND (20ns transient) | –5 | V | ||
HB1 to SW1, HB2 to SW2 | –0.3 | 6.5 | V | |
HB1 to SW1, HB2 to SW2 (20ns transient) | –5 | V | ||
HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2 | –0.3 | HB + 0.3 | V | |
HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2 (20ns transient) | –5 | V | ||
LO1, LOL1, LO2, LOL2 to PGND | –0.3 | VCC + 0.3 | V | |
LO1, LOL1, LO2, LOL2 to PGND ( 20ns transient) | –1.5 | VCC + 0.3 | V | |
OSC, SS1, SS2, COMP1, COMP2, RES, DEMB, ILSET | –0.3 | VDDA + 0.3 | V | |
EN1, EN2 to PGND | –0.3 | 70 | V | |
VCC, VCCX, VDDA, PG1, PG2, FB1, FB2, SYNIN | –0.3 | 6.5 | V | |
VOUT1, VOUT2, CS1, CS2 | –0.3 | 15.5 | V | |
VOUT1 to CS1, VOUT2 to CS2 | –0.3 | 0.3 | V | |
PGND to AGND | –0.3 | 0.3 | V | |
Operating junction temperature(2) | –40 | 150 | ºC | |
Storage temperature, Tstg | –40 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1)(2) | ±2000 | V | |
Charged-device model (CDM), per AEC Q100-011(3) | All pins except 1, 10, 11, 20, 21, 30, 31, and 40 | ±500 | |||
Pins 1, 10, 11, 20, 21, 30, 31, and 40 | ±750 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VIN | Input voltage | VIN | 3.8 | 65 | V | |
SW1, SW2 to PGND | –0.3 | 65 | V | |||
HB1 to SW1, HB2 to SW2 | –0.3 | 5 | 5.25 | V | ||
HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2 | –0.3 | HB + 0.3 | V | |||
LO1, LOL1, LO2, LOL2 to PGND | –0.3 | 5 | 5.25 | V | ||
FB1, FB2, PG1, PG2, SYNIN, OSC, SS1, SS2, RES, DEMB, VCCX, ILSET | –0.3 | 5 | V | |||
EN1, EN2 to PGND | –0.3 | 65 | V | |||
VCC, VDDA | –0.3 | 5 | 5.25 | V | ||
VOUT1, VOUT2, CS1, CS2 | 1.5 | 5 | 15 | V | ||
VO | Output voltage | SYNOUT | –0.3 | 5.25 | V | |
PGND to AGND | –0.3 | 0.3 | V | |||
TJ | Operating junction temperature(2) | –40 | 150 | °C |
THERMAL METRIC(1) | LM5140-Q1 | UNIT | |
---|---|---|---|
RWG (VQFN) | |||
40 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 34.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 22.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 9.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 9.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.3 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIN SUPPLY VOLTAGE | ||||||
I(SHUTDOWN) | Shutdown mode current | VIN 8 V- 18 V, EN1 = 0 V, EN2 = 0 V, VCCX = 0 V | 9 | 12.5 | µA | |
I(STANDBY) | Standby current | EN1 = 5 V, EN2 = 0 V, VOUT1, in regulation, no-load, not switching. VIN 8 V - 18 V. DEMB = GND |
35 | µA | ||
Or EN1 = 0 V, EN2 = 5 V, VOUT2 in regulation, no-load, not switching, VOUT2 connected to VCCX, DEMB = GND. |
42 | µA | ||||
VCC REGULATOR | ||||||
VCC(REG) | VCC regulation voltage | VIN = 6 V - 18 V, 0 - 150 mA, VCCX = 0 V |
4.75 | 5 | 5.25 | V |
VCC(UVLO) | VCC under voltage threshold | VCC rising, VCCX = 0 V | 3.25 | 3.4 | 3.55 | V |
VCC(HYST) | VCC hysteresis voltage | VCCX = 0 V | 175 | mV | ||
ICC(LIM) | VCC sourcing current limit | VCCX = 0 V | 170 | 250 | mA | |
VDDA | ||||||
VDDA(REG) | Internal bias supply power | VCCX = 0 V | 4.75 | 5 | 5.25 | V |
VDDA(UVLO) | VDDA undervoltage lockout | VCC rising, VCCX = 0 V | 3.1 | 3.2 | 3.3 | V |
VDDA(HYST) | VDDA hysteresis voltage | VCCX = 0 V | 180 | mV | ||
R(VDDA) | VDDA resistance | VCCX = 0 V | 50 | Ω | ||
VCCX | ||||||
VCCX(ON) | VCC(ON) threshold | VCC rising | 4.1 | 4.3 | 4.4 | V |
R(VCCX) | VCCX resistance | VCCX = 5 V | 1 | Ω | ||
VCCX(HYST) | VCCX hysteresis voltage | 200 | mV | |||
OSCILLATOR SELECT THRESHOLDS | ||||||
2.2-MHz Oscillator select threshold | (OSC pin) | 2.4 | V | |||
440-kHz Oscillator select threshold | (OSC pin) | 0.4 | V | |||
CURRENT LIMIT | ||||||
V(CS1) | Current limit threshold1 | ILSET = VDDA, Measure from CS to VOUT |
66 | 73 | 80 | mV |
V(CS2) | Current limit threshold2 | ILSET = GND, Measure from CS to VOUT |
44 | 48 | 53 | mV |
Current sense delay to output | 40 | ns | ||||
Current sense amplifier gain | 11.4 | 12 | 12.6 | V/V | ||
ICS(BIAS) | Amplifier input bias | 10 | nA | |||
75-mV current limit select threshold (ILSET) | 2.4 | V | ||||
75-mV current limit select threshold (ILSET) | 0.4 | V | ||||
RES | ||||||
I(RES) | RES current source | 20 | µA | |||
V(RES) | RES threshold | 1.2 | V | |||
Timer hIccup mode fault | 512 | cycles | ||||
RDS(ON) | RES pulldown | 5 | Ω | |||
OUTPUT VOLTAGE REGULATION | ||||||
3.3 V | VIN = 3.8 V - 42 V | 3.273 | 3.3 | 3.327 | V | |
5 V | VIN = 5.5 V - 42 V | 4.95 | 5 | 5.05 | V | |
8 V | VIN = 8.5 V - 42 V | 7.92 | 8 | 8.08 | V | |
FEEDBACK | ||||||
VOUT1 select threshold 3.3-V Output | VDDA – 0.3 | V | ||||
VOUT2 select threshold 5 V | VDDA – 0.3 | V | ||||
Regulated Feedback Voltage | 1.19 | 1.2 | 1.21 | V | ||
FB(LOWRES) | Resistance to ground on FB for FB=0 detection | 500 | Ω | |||
FB(EXTRES) | Thevenin equivalent resistance at FB for external regulation detection | FB < 2 V | 5 | kΩ | ||
TRANSCONDUCTANCE AMPLIFIER | ||||||
Gm | Gain | Feedback to COMP | 1010 | 1200 | µS | |
FB | Input Bias Current | 15 | nA | |||
Transconductance Amplifier source current | COMP = 1 V, FB = 1.0 V | 100 | µA | |||
Transconductance Amplifier sink current | COMP = 1 V, FB = 1.4 V | 100 | µA | |||
POWER GOOD | ||||||
PG(UV) | PG1 and PG2 Under Voltage trip levels | Falling with respect to the regulation voltage | 90% | 92% | 94% | |
PG(OVP) | PG1 and PG2 Over Voltage trip levels | Rising with respect to the regulation voltage | 108% | 110% | 112% | |
PG(HYST) | Power Good hysteresis voltage | 3.4% | ||||
PG(VOL) | PG1 and PG2 | Open Collector, Isink = 2 mA | 0.4 | V | ||
PG(rdly) | OV Filter Time | VOUT rising | 25 | µs | ||
PG(fdly) | UV Filter Time | VOUT falling | 30 | µs | ||
HO GATE DRIVER | ||||||
VOLH | HO Low-state output voltage | IHO = 100 mA | 0.05 | V | ||
VOHH | HO High-state output voltage | IHO = -100 mA, VOHH = VHB - VHO | 0.07 | V | ||
trHO | HO rise time (10% to 90%) | CLOAD = 2700 pf | 4 | ns | ||
tfHO | HO fall time (90% to 10%) | CLOAD = 2700 pf | 3 | ns | ||
IOHH | HO peak source current | VHO = 0 V, SW = 0 V, HB = 5 V, VCCX = 5 V | 3.25 | Apk | ||
IOLH | HO peak sink current | VCCX = 5 V | 4.25 | Apk | ||
V(BOOT) | UVLO | HO falling | 2.5 | V | ||
Hysteresis | 110 | mV | ||||
I(BOOT) | Quiescent current | 3 | µA | |||
LO GATE DRIVER | ||||||
VOLL | LO Low-state Output Voltage | ILO = 100 mA | 0.05 | V | ||
VOHL | LO High-state Output voltage | ILO = -100 mA, VOHL = VCC - VLO | 0.07 | V | ||
trLO | LO rise time (10% to 90%) | CLOAD = 2700 pf | 4 | ns | ||
tfLO | LO fall time (90% to 10%) | CLOAD = 2700 pf | 3 | ns | ||
IOHL | LO peak source current | VCCX = 5 V | 3.25 | Apk | ||
IOLL | LO peak sink current | VCCX = 5 V | 4.25 | Apk | ||
ADAPTIVE DEAD TIME CONTROL | ||||||
V(GS-DET) | VGS detection threshold | VGS falling, no-load | 2.5 | V | ||
tdly1 | HO off to LO on dead time | 20 | ns | |||
tdly2 | LO off to HO on dead time | 15 | ns | |||
DIODE EMULATION | ||||||
VIL | DEM input low threshold | 0.4 | V | |||
VIH | FPWM input high threshold | 2.4 | V | |||
SW | zero cross threshold | –5 | mV | |||
ENABLE INPUTS EN1 AND EN2 | ||||||
VIL | Enable input low threshold | VCCX = 0 V | 0.4 | V | ||
VIH | Enable input high threshold | VCCX = 0 V | 2.4 | V | ||
Ilkg | Leakage | EN1, EN2 logic inputs only | 1 | µA | ||
SYN INPUT | ||||||
VIL | SYNIN input low threshold | 0.4 | V | |||
VIH | SYNIN input high threshold | 2.4 | V | |||
SYNIN input low frequency range 440 kHz | 350 | 550 | kHz | |||
SYNIN input low frequency range 2.2 MHz | 1800 | 2600 | kHz | |||
SYN OUTPUT | ||||||
VOH | SYN output high output voltage | Source -16 mA, VDDA = 5 V | 2.4 | V | ||
VOL | SYN Output low level output voltage | Sink 16 mA | 0.4 | V | ||
Phase between HO1 and HO2 | 180 | degrees | ||||
Duty Cycle | 50% | |||||
SOFT-START | ||||||
ISS | Soft-start current | 16 | 22 | 28 | µA | |
RDS(ON) | Soft-start pulldown resistance | 3 | Ω | |||
THERMAL | ||||||
TSD thermal shutdown | 175 | ºC | ||||
Thermal shutdown hysteresis | 15 | ºC |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Oscillator frequency, 2.2 MHz | OSC = VDDA, VIN = 8 V – 18 V | 2060 | 2200 | 2340 | kHz | |
Oscillator frequency, 440 kHz | OSC = GND, VIN = 8 V – 18 V | 410 | 440 | 470 | kHz | |
ton | Minimum on-time | 45 | ns | |||
toff | Minimum off-time | 100 | ns |
VIN 8-18 V | EN1 = EN2 = 12 V | 2.2 MHz |
VIN 8-18 V | EN1 = EN2 = 12 V |
VIN 6-18V | EN1 = EN2 = 12 V |
VCC Rising | EN1 = EN2 = 12 V |
VIN = 12 V | VCC Rising |
VIN = 12 V | ILSET = GND |
VIN 12 V | EN1 = 12 V | EN2 = GND |
VIN 12 V | OSC = VCC |
VIN 18 V |
VIN 8-18 V | EN1 = EN2 = 12 V | 2.2 MHz |
VIN 8-18 V | EN1 = 12 V, EN2 = 0 V | 2.2 MHz |
VCC Rising | EN1 = EN2 = 12 V |
VCC Rising |
VIN = 12 V | ILSET = VCC |
VCC Rising |
VIN 5.5 V - 42 V | EN1 = GND | EN2 = 12 V |
VIN 12 V | OSC = GND |
VIN 3.8 V |