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LM98640QML-SP Radiation Hardness Assured (RHA), Dual Channel, 14-Bit, 40-MSPS Analog Front End With LVDS Output
SNAS461G
May 2010 – November 2018
LM98640QML-SP
PRODUCTION DATA.
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LM98640QML-SP Radiation Hardness Assured (RHA), Dual Channel, 14-Bit, 40-MSPS Analog Front End With LVDS Output
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Quality Conformance Inspection
6.6
LM98640QML-SP Electrical Characteristics
6.7
AC Timing Specifications
6.8
Typical Performance Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Input Sampling Modes
7.3.1.1
Sample & Hold Mode
7.3.1.1.1
Sample & Hold Mode CLAMP/SAMPLE Adjust
7.3.1.2
CDS Mode
7.3.1.2.1
CDS Mode Bimodal Offset
7.3.1.2.2
CDS Mode CLAMP/SAMPLE Adjust
7.3.2
Input Bias and Clamping
7.3.2.1
Sample and Hold Mode Biasing
7.3.2.2
CDS Mode Biasing
7.3.2.3
VCLP DAC
7.3.3
Programmable Gain
7.3.3.1
CDS/SH Stage Gain
7.3.3.2
PGA Gain Plots
7.3.4
Programmable Analog Offset Correction
7.3.5
Analog to Digital Converter
7.3.6
LVDS Output
7.3.6.1
LVDS Output Voltage
7.3.6.2
LVDS Output Modes
7.3.6.3
TXFRM Output
7.3.6.3.1
Output Mode 1 - Dual Lane
7.3.6.3.2
Output Mode 2 - Quad Lane
7.3.7
Clock Receiver
7.3.8
Power Trimming
7.4
Device Functional Mode
7.4.1
Powerdown Modes
7.4.2
LVDS Test Modes
7.4.2.1
Test Mode 0 - Fixed Pattern
7.4.2.2
Test Mode 1 - Horizontal Gradient
7.4.2.3
Test Mode 2 - Vertical Gradient
7.4.2.4
Test Mode 3 - Lattice Pattern
7.4.2.5
Test Mode 4 - Stripe Pattern
7.4.2.6
Test Mode 5 - LVDS Test Pattern (Synchronous)
7.4.2.7
Test Mode 6 - LVDS Test Pattern (Asynchronous)
7.4.2.8
Pseudo Random Number Mode
7.5
Programming
7.5.1
Serial Interface
7.5.2
Writing to the Serial Registers
7.5.3
Reading the Serial Registers
7.5.4
Serial Interface Timing Details
7.6
Register Maps
7.6.1
Register Definitions
8
Application and Implementation
8.1
Application Information
8.1.1
Total Ionizing Dose
8.1.2
Single Event Latch-Up and Functional Interrupt
8.1.3
Single Event Effects
8.2
Typical Application
8.2.1
Sample/Hold Mode
8.3
Initialization Set Up
9
Layout
9.1
Layout Guidelines
9.1.1
Power Planes
9.1.2
Bypass Capacitors
9.1.3
Ground Plane
9.1.4
Thermal Management
10
Device and Documentation Support
10.1
Device Support
10.1.1
Development Support
10.1.1.1
Evaluation Board
10.1.1.2
Register Programming Software
10.2
Receiving Notification of Documentation Updates
10.3
Community Resources
10.4
Export Control Notice
10.5
Trademarks
10.6
Electrostatic Discharge Caution
10.7
Glossary
11
Mechanical, Packaging, and Orderable Information
11.1
Engineering Samples
IMPORTANT NOTICE
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メカニカル・データ(パッケージ|ピン)
NBB|68
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DATA SHEET
LM98640QML-SP Radiation Hardness Assured (RHA), Dual Channel, 14-Bit, 40-MSPS Analog Front End With LVDS Output
1
Features
Radiation Hardened
TID 100 krad(Si)
Single Event Latch-Up (SEL) Immune to LET = 120 MeV-cm
2
/mg
Single Event Functional Interrupt (SEFI) Free to 120 MeV-cm
2
/mg
SMD 5962R1820301VXC
ADC Resolution: 14-Bit
ADC Sampling Rate: 5 MSPS to 40 MSPS
Input Level: 2.85 V
Supply Voltages 3.3 V and 1.8 V (Nominal)
125 mW per Channel at 15 MSPS
178 mW per Channel at 40 MSPS
CDS or S/H Processing for CCD or CIS Sensors
CDS or S/H Gain 0 dB or 6 dB
Programmable Analog Gain for Each Channel
256 Steps; Range –3 dB to 18 dB
Programmable Analog Offset Correction
Fine and Coarse DAC Resolution ±8 Bits
Fine DAC Range ±5 mV
Coarse DAC Range ±250 mV
Programmable Input Clamp Voltage
Programmable Sample Edge: 1/64th Pixel Period
INL at 15 MHz: ±3.5 LSB
Noise Floor: –79 dB
Crosstalk: –80 dB
Operating Temp: –55°C to 125°C
2
Applications
Space Satellites Scientific Applications
Focal Plane Electronics
Imaging Attitude Control Systems
Earth Imaging