SNAS254B October   2006  – April 2017 LM98714

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 AC Timing Specifications
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Clock Introduction
      2. 7.3.2  Modes of Operation
        1. 7.3.2.1 Mode 3 - Three Channel Input/Synchronous Pixel Sampling
        2. 7.3.2.2 Mode 2 - Two Channel Input/Synchronous Pixel Sampling
        3. 7.3.2.3 Mode 1a - One Channel Input/One, Two, Three, Four, or Five Color Sequential Line Sampling
        4. 7.3.2.4 Mode 1b - One Channel Input Per Line/Sequential Line (Input) Sampling/Three Channel Processing
      3. 7.3.3  Input Bias and Clamping
        1. 7.3.3.1 CDS Mode
        2. 7.3.3.2 Input Source Follower Buffers
        3. 7.3.3.3 VCLP DAC
      4. 7.3.4  Coarse Pixel Phase Alignment
      5. 7.3.5  Internal Sample Timing
      6. 7.3.6  Automatic Black Level Correction Loop
        1. 7.3.6.1 Black Level Offset DAC
        2. 7.3.6.2 Black Level Clamp (BLKCLP)
        3. 7.3.6.3 Pixel Averaging
        4. 7.3.6.4 Target Black Level
        5. 7.3.6.5 Offset Integration
        6. 7.3.6.6 Line Averaging
      7. 7.3.7  Internal Timing Generation
        1. 7.3.7.1 Pix Signal Generator OR/NOR Modes
        2. 7.3.7.2 SH2 and SH3 Generation
      8. 7.3.8  CCD Timing Generator Master/Slave Modes
        1. 7.3.8.1 Master Timing Generator Mode
        2. 7.3.8.2 Slave Timing Generator Mode
      9. 7.3.9  LVDS Output Mode
        1. 7.3.9.1 LVDS Output Format
        2. 7.3.9.2 LVDS Output Timing Details
        3. 7.3.9.3 LVDS Control Bit Coding
        4. 7.3.9.4 LVDS Data Latency Diagrams
        5. 7.3.9.5 LVDS Test Modes
          1. 7.3.9.5.1 Test Mode 1 - Worst Case Transitions
          2. 7.3.9.5.2 Test Mode 2 - Ramp
          3. 7.3.9.5.3 Test Mode 3 - Fixed Output Data
      10. 7.3.10 CMOS Output Mode
        1. 7.3.10.1 CMOS Output Data Format
      11. 7.3.11 CMOS Output Data Latency Diagrams
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode 3 - Three Channel Input/Synchronous Pixel Sampling
      2. 7.4.2 Mode 2 - Two Channel Input/Synchronous Pixel Sampling
      3. 7.4.3 Mode 1a - One Channel Input/One, Two, Three, Four, Or Five Color Sequential Line Sampling
      4. 7.4.4 Mode 1b - One Channel Color Input Per Line/Sequential Line (Input) Sampling/Three Channel Processing
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Writing To The Serial Registers
        2. 7.5.1.2 Reading The Serial Registers
        3. 7.5.1.3 Serial Interface Timing Details
    6. 7.6 Register Maps
      1. 7.6.1 Configuration Registers
      2. 7.6.2 Register Definition
  8. 8 Application and Implementation
    1. 8.1 Typical Application
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Device Support
        1. 9.1.1.1 Development Support
      2. 9.1.2 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • LVDS/CMOS Outputs
  • LVDS/CMOS Pixel Rate Input Clock or ADC Input Clock
  • CDS or S/H Processing for CCD or CIS Sensors
  • Independent Gain/Offset Correction for Each Channel
  • Digital Black Level Correction Loop for Each Channel
  • Programmable Input Clamp Voltage
  • Flexible CCD/CIS Sensor Timing Generator
  • Key Specifications
    • Maximum Input Level: 1.2 or 2.4 Volt Modes
      • (Both with + or – Polarity Option)
    • ADC Resolution: 16-Bit
    • ADC Sampling Rate: 45 MSPS
    • INL: ±23 LSB (Typ)
    • Channel Sampling Rate: 15/22.5/30 MSPS
    • PGA Gain Steps: 256 Steps
    • PGA Gain Range: 0.7 to 7.84x
    • Analog DAC Resolution: ±9 Bits
    • Analog DAC Range: ±300 mV or ±600 mV
    • Digital DAC Resolution: ±6 Bits
    • Digital DAC Range: –1024 LSB to + 1008 LSB
    • SNR: –74dB (at 0 dB PGA Gain)
    • Power Dissipation: 505 mW (LVDS) 610 mW (CMOS)
    • Operating Temp: 0 to 70°C
    • Supply Voltage: 3.3 V Nominal (3.0 V to 3.6 V Range)

2 Applications

  • Multi-Function Peripherals
  • Facsimile Equipment
  • Flatbed or Handheld Color Scanners
  • High-Speed Document Scanner

3 Description

The LM98714 is a fully integrated, high performance 16-Bit, 45 MSPS signal processing solution for digital color copiers, scanners, and other image processing applications. High-speed signal throughput is achieved with an innovative architecture utilizing Correlated Double Sampling (CDS), typically employed with CCD arrays, or Sample and Hold (S/H) inputs (for Contact Image Sensors and CMOS image sensors). The signal paths utilize 8 bit Programmable Gain Amplifiers (PGA), a ±9-Bit offset correction DAC and independently controlled Digital Black Level correction loops for each input. The PGA and offset DAC are programmed independently allowing unique values of gain and offset for each of the three inputs. The signals are then routed to a 45 MHz high performance analog-to-digital converter (ADC). The fully differential processing channel shows exceptional noise immunity, having a very low noise floor of –74dB. The 16-bit ADC has excellent dynamic performance making the LM98714 transparent in the image reproduction chain.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LM98714 TSSOP (48) 12.50 mm × 6.1 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

System Block Diagram

LM98714 20105370.gif