SNOSDI8
May 2024
LMG2650
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
6
Parameter Measurement Information
6.1
GaN Power FET Switching Parameters
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
GaN Power FET Switching Capability
7.3.2
Turn-On Slew-Rate Control
7.3.3
Current-Sense Emulation
7.3.4
Bootstrap Diode Function
7.3.5
Input Control Pins (EN, INL, INH, GDH)
7.3.6
INL - INH Interlock
7.3.7
AUX Supply Pin
7.3.7.1
AUX Power-On Reset
7.3.7.2
AUX Under-Voltage Lockout (UVLO)
7.3.8
BST Supply Pin
7.3.8.1
BST Power-On Reset
7.3.8.2
BST Under-Voltage Lockout (UVLO)
7.3.9
Overcurrent Protection
7.3.10
Overtemperature Protection
7.3.11
Fault Reporting
7.4
Device Functional Modes
8
Device and Documentation Support
8.1
Receiving Notification of Documentation Updates
8.2
Support Resources
8.3
Trademarks
8.4
Electrostatic Discharge Caution
8.5
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RFB|19
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snosdi8_oa
Data Sheet
LMG2650
650V
95
mΩ GaN Half Bridge with Integrated Driver and Current Sense Emulation