SNOSDA8C October 2020 – February 2024 LMG3422R050 , LMG3426R050
PRODUCTION DATA
The LMG342xR050 GaN FET with integrated driver and protection is targeted at switch-mode power converters and enables designers to achieve new levels of power density and efficiency.
The LMG342xR050 integrates a silicon driver that enables switching speed up to 150V/ns. TI’s integrated precision gate bias results in higher switching SOA compared to discrete silicon gate drivers. This integration, combined with TI's low-inductance package, delivers clean switching and minimal ringing in hard-switching power supply topologies. Adjustable gate drive strength allows control of the slew rate from 20V/ns to 150V/ns, which can be used to actively control EMI and optimize switching performance. The LMG3426R050 includes the zero-voltage detection (ZVD) feature which provides a pulse output from the ZVD pin when zero-voltage switching is realized.
Advanced power management features include digital temperature reporting and fault detection. The temperature of the GaN FET is reported through a variable duty cycle PWM output, which simplifies managing device loading. Faults reported include overcurrent, short-circuit, overtemperature, VDD UVLO, and high-impedance RDRV pin.
PART NUMBER | ZERO-VOLTAGE DETECTION FEATURE |
---|---|
LMG3422R050 | — |
LMG3426R050 | Yes |
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | LMG3422R050 | LMG3426R050 | ||
NC1 | 1, 16 | 1, 16 | — | Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to DRAIN. |
DRAIN | 2–15 | 2–15 | P | GaN FET drain. Internally connected to NC1. |
NC2 | 17, 54 | 17, 54 | — | Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to SOURCE, GND, and THERMAL PAD. |
SOURCE | 18–40 | 18–40 | P | GaN FET source. Internally connected to GND, NC2, and THERMAL PAD. |
VNEG | 41–42 | 41–42 | P | Internal buck-boost converter negative output. Used as the negative supply to turn off the depletion mode GaN FET. Bypass to ground with a 2.2µF capacitor. |
BBSW | 43 | 43 | P | Internal buck-boost converter switch pin. Connect an inductor from this point to ground. |
GND | 44, 45, 49 | 44, 45, 49 | G | Signal ground. Internally connected to SOURCE, NC2, and THERMAL PAD. |
VDD | 46 | 46 | P | Device input supply. |
IN | 47 | 47 | I | CMOS-compatible non-inverting input used to turn the FET on and off. |
FAULT | 48 | 48 | O | Push-pull digital output that asserts low during a fault condition. Refer to Fault Detection for details. |
OC | 50 | — | O | Push-pull digital output that asserts low during overcurrent and short-circuit fault conditions. Refer to Fault Detection for details. |
ZVD | — | 50 | O | Push-pull digital output that provides zero-voltage detection signal to indicate if device achieves zero-voltage switching in current switching cycle. Refer to Section 7.3.11 for details. |
TEMP | 51 | 51 | O | Push-pull digital output that gives information about the GaN FET temperature. Outputs a fixed 9kHz pulsed waveform. The device temperature is encoded as the duty cycle of the waveform. |
RDRV | 52 | 52 | I | Drive-strength selection pin. Connect a resistor from this pin to GND to set the turn-on drive strength to control slew rate. Tie the pin to GND to enable 150V/ns and tie the pin to LDO5V to enable 100V/ns. |
LDO5V | 53 | 53 | P | 5V LDO output for external digital isolator. |
THERMAL PAD | — | — | — | Thermal pad. Internally connected to SOURCE, GND, and NC2. The thermal pad can be used to conduct rated device current. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VDS | Drain-source voltage, FET off | 600 | V | ||
VDS(surge) | Drain-source voltage, FET switching, surge condition(2) | 720 | V | ||
VDS(tr)(surge) | Drain-source transient ringing peak voltage, FET off, surge condition(2)(3) | 800 | V | ||
Pin voltage | VDD | –0.3 | 20 | V | |
LDO5V | –0.3 | 5.5 | V | ||
VNEG | –16 | 0.3 | V | ||
BBSW | VVNEG–1 | VVDD+0.5 | V | ||
IN | –0.3 | 20 | V | ||
FAULT, OC, TEMP | –0.3 | VLDO5V+0.3 | V | ||
RDRV | –0.3 | 5.5 | V | ||
ID(RMS) | Drain RMS current, FET on | 44 | A | ||
ID(pulse) | Drain pulsed current, FET on, tp < 10µs(4) | –96 | Internally Limited | A | |
IS(pulse) | Source pulsed current, FET off, tp < 1µs | 60 | A | ||
TJ | Operating junction temperature(5) | –40 | 150 | °C | |
Tstg | Storage temperature | –55 | 150 | °C |
PARAMETER | VALUE | UNIT | ||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) | ±500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
Supply voltage | VDD (Maximum switching frequency derated for VVDD < 9V) |
7.5 | 12 | 18 | V | |
Input voltage | IN | 0 | 5 | 18 | V | |
ID(RMS) | Drain RMS current | 32 | A | |||
Positive source current | LDO5V | 25 | mA | |||
RRDRV | RDRV to GND resistance from external slew-rate control resistor | 0 | 500 | kΩ | ||
CVNEG | VNEG to GND capacitance from external bypass capacitor | 1 | 10 | uF | ||
LBBSW | BBSW to GND inductance from external buck-boost inductor (1) | 3 | 4.7 | 10 | uH |
THERMAL METRIC(1) | LMG342xR050 | UNIT | |
---|---|---|---|
RQZ (VQFN) | |||
54 PINS | |||
RθJC(bot,avg) | Junction-to-case (bottom) average thermal resistance | 0.88 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
GAN POWER TRANSISTOR | ||||||
RDS(on) | Drain-source on resistance | VIN = 5V, TJ = 25°C | 43 | 55 | mΩ | |
VIN = 5V, TJ = 125°C | 73 | mΩ | ||||
VSD | Third-quadrant mode source-drain voltage | IS = 0.1A | 3.8 | V | ||
IS = 15A | 3 | 5.3 | V | |||
IDSS | Drain leakage current | VDS = 600V, TJ = 25°C | 1 | uA | ||
VDS = 600V, TJ = 125°C | 7 | uA | ||||
COSS | Output capacitance | VDS = 400V | 110 | pF | ||
CO(er) | Energy related effective output capacitance | VDS = 0V to 400V | 155 | pF | ||
CO(tr) | Time related effective output capacitance | 235 | pF | |||
QOSS | Output charge | 100 | nC | |||
QRR | Reverse recovery charge | 0 | nC | |||
VDD – SUPPLY CURRENTS | ||||||
VDD quiescent current (LMG3422) | VVDD = 12V, VIN = 0V or 5V | 700 | 1200 | uA | ||
VDD quiescent current (LMG3425) | VVDD = 12V, VIN = 0V or 5V | 780 | 1300 | uA | ||
VDD operating current | VVDD = 12V, fIN = 140kHz, soft-switching | 9 | 10.5 | mA | ||
BUCK BOOST CONVERTER | ||||||
VNEG output voltage | VNEG sinking 40mA | –14 | V | |||
IBBSW,PK(low) | Peak BBSW sourcing current at low peak current mode setting (Peak external buck-boost inductor current) |
0.3 | 0.4 | 0.5 | A | |
IBBSW,PK(high) | Peak BBSW sourcing current at high peak current mode setting (Peak external buck-boost inductor current) |
0.8 | 1 | 1.2 | A | |
High peak current mode setting enable – IN positive-going threshold frequency | 280 | 420 | 515 | kHz | ||
LDO5V | ||||||
Output voltage | LDO5V sourcing 25mA | 4.75 | 5 | 5.25 | V | |
Short-circuit current | 25 | 50 | 100 | mA | ||
IN | ||||||
VIN,IT+ | Positive-going input threshold voltage | 1.7 | 1.9 | 2.45 | V | |
VIN,IT– | Negative-going input threshold voltage | 0.7 | 1 | 1.3 | V | |
Input threshold hysteresis | 0.7 | 0.9 | 1.3 | V | ||
Input pulldown resistance | VIN = 2V | 100 | 150 | 200 | kΩ | |
FAULT, OC, TEMP – OUPUT DRIVE | ||||||
Low-level output voltage | Output sinking 8mA | 0.16 | 0.4 | V | ||
High-level output voltage | Output sourcing 8mA, Measured as VLDO5V – VO |
0.2 | 0.45 | V | ||
VDD, VNEG – UNDER VOLTAGE LOCKOUT | ||||||
VVDD,T+(UVLO) | VDD UVLO – positive-going threshold voltage | 6.5 | 7 | 7.5 | V | |
VDD UVLO – negative-going threshold voltage | 6.1 | 6.5 | 7 | V | ||
VDD UVLO – Input threshold voltage hysteresis | 510 | mV | ||||
VNEG UVLO – negative-going threshold voltage | –13.6 | –13.0 | –12.3 | V | ||
VNEG UVLO – positive-going threshold voltage | –13.2 | –12.75 | –12.1 | V | ||
GATE DRIVER | ||||||
Turn-on slew rate | From VDS < 320V to VDS < 80V, RDRV disconnected from LDO5V, RRDRV = 300kΩ, TJ = 25℃, VBUS = 400V, LHB current = 10A, see Figure 6-1 | 20 | V/ns | |||
From VDS < 320V to VDS < 80V, RDRV tied to LDO5V, TJ = 25℃, VBUS = 400V, LHB current = 10A, see Figure 6-1 | 100 | V/ns | ||||
From VDS < 320V to VDS < 80V, RDRV disconnected from LDO5V, RRDRV = 0Ω, TJ = 25℃, VBUS = 400V, LHB current = 10A, see Figure 6-1 | 150 | V/ns | ||||
Maximum GaN FET switching frequency. | VNEG rising to > –13.25V, soft-switched, maximum switching frequency derated for VVDD < 9V | 3.6 | MHz | |||
FAULTS | ||||||
IT(OC) | DRAIN overcurrent fault – threshold current | 40 | 50 | 60 | A | |
IT(SC) | DRAIN short-circuit fault – threshold current | 60 | 75 | 90 | A | |
di/dtT(SC) | di/dt threshold between overcurrent and short-circuit faults | 150 | A/µs | |||
GaN temperature fault – postive-going threshold temperature | 175 | °C | ||||
GaN Temperature fault – threshold temperature hysteresis | 30 | °C | ||||
Driver temperature fault – positive-going threshold temperature | 185 | °C | ||||
Driver Temperature fault – threshold temperature hysteresis | 20 | °C | ||||
TEMP | ||||||
Output Frequency | 4.5 | 9 | 14 | kHz | ||
Output PWM Duty Cycle | GaN TJ = 150℃ | 82 | % | |||
GaN TJ = 125℃ | 58.5 | 64.6 | 70 | % | ||
GaN TJ = 85℃ | 36.2 | 40 | 43.7 | % | ||
GaN TJ = 25℃ | 0.3 | 3 | 6 | % | ||
IDEAL-DIODE MODE CONTROL | ||||||
VT(3rd) | Drain-source third-quadrant detection – threshold voltage | –0.15 | 0 | 0.15 | V | |
IT(ZC) | Drain zero-current detection – threshold current | 0℃ ≤ TJ ≤ 125℃ | –0.2 | 0 | 0.2 | A |
–40℃ ≤ TJ ≤ 0℃ | –0.35 | 0 | 0.35 | A |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SWITCHING TIMES | ||||||
td(on)(Idrain) | Drain-current turn-on delay time | From VIN > VIN,IT+ to ID > 1A, VBUS = 400V, LHB current = 10A, see Figure 6-1 and Figure 6-2 | 28 | 42 | ns | |
td(on) | Turn-on delay time | From VIN > VIN,IT+ to VDS < 320V, VBUS = 400V, LHB current = 10A, see Figure 6-1 and Figure 6-2 | 32 | 52 | ns | |
tr(on) | Turn-on rise time | From VDS < 320V to VDS < 80V, VBUS = 400V, LHB current = 10A, see Figure 6-1 and Figure 6-2 | 2.5 | 4 | ns | |
td(off) | Turn-off delay time | From VIN < VIN,IT– to VDS > 80V, VBUS = 400V, LHB current = 10A, see Figure 6-1 and Figure 6-2 | 44 | 65 | ns | |
tf(off) | Turn-off fall time(1) | From VDS > 80V to VDS > 320V, VBUS = 400V, LHB current = 10A, see Figure 6-1 and Figure 6-2 | 21 | ns | ||
Minimum IN high pulse-width for FET turn-on | VIN rise/fall times < 1ns, VDS falls to < 200V, VBUS = 400V, LHB current = 10A, see Figure 6-1 | 24 | ns | |||
STARTUP TIMES | ||||||
t(start) | Driver start-up time | From VVDD > VVDD,T+(UVLO) to FAULT high, CLDO5V = 100nF, CVNEG = 2.2µF at 0V bias linearly decreasing to 1.5µF at 15V bias | 310 | 470 | us | |
FAULT TIMES | ||||||
toff(OC) | Overcurrent fault FET turn-off time, FET on before overcurrent | VIN = 5V, From ID > IT(OC) to ID < 50A, ID di/dt = 100A/µs | 110 | 145 | ns | |
toff(SC) | Short-circuit current fault FET turn-off time, FET on before short circuit | VIN = 5V, From ID > IT(SC) to ID < 50A, ID di/dt = 700A/µs | 65 | 100 | ns | |
Overcurrent fault FET turn-off time, FET turning on into overcurrent | From ID > IT(OC) to ID < 50A | 200 | 250 | ns | ||
Short-circuit fault FET turn-off time, FET turning on into short circuit | From ID > IT(SC) to ID < 50A | 100 | 180 | ns | ||
IN reset time to clear FAULT latch | From VIN < VIN,IT– to FAULT high | 250 | 380 | 580 | us | |
t(window)(OC) | Overcurrent fault to short-circuit fault window time | 50 | ns | |||
IDEAL-DIODE MODE CONTROL TIMES | ||||||
Overtemperature-shutdown ideal-diode mode IN falling blanking time | 150 | 230 | 360 | ns | ||
ZERO VOLTAGE DETECTION TIMES | ||||||
tWD_ZVD | ZVD Pulse Width | See Figure 6-3 | 75 | 100 | 140 | ns |
tDL_ZVD | Time delay between IN rise to ZVD pulse's rising edge | See Figure 6-3 | 15 | 30 | ns | |
t3rd_ZVD | 3rd quadrant conduction time when the ZVD pulse starts to appear | Vbus = 10V, IL = 5A, Rdrv = 5V, measure the 3rd quadrant conduction time when the ZVD pulse starts to appear. See Figure 6-3 | 42 | 56 | ns |
VDD = 12V | TJ = 25°C |
IN = 0V |
VDD = 12V | TJ = 125°C |
Figure 6-1 shows the circuit used to measure most switching parameters. The top device in this circuit is used to re-circulate the inductor current and functions in third-quadrant mode only. The bottom device is the active device that turns on to increase the inductor current to the desired test current. The bottom device is then turned off and on to create switching waveforms at a specific inductor current. Both the drain current (at the source) and the drain-source voltage is measured. Figure 6-2 shows the specific timing measurement. TI recommends to use the half-bridge as a double pulse tester. Excessive third-quadrant operation can overheat the top device.