The LMH1219 is a low-power, dual-input and dual-output, adaptive equalizer with integrated reclocker. It supports SMPTE video rates up to 11.88 Gbps and 10 GbE video over IP, enabling UHD video for 4K/8K applications. An extended reach adaptive cable equalizer at IN0 is designed to equalize data transmitted over 75 Ω coaxial cable and operates over a wide range of data rates from 125 Mbps to 11.88 Gbps. An adaptive board trace equalizer at IN1 is SFF-8431 compatible and supports both SMPTE and 10 GbE data rates.
The integrated reclocker attenuates high frequency jitter and provides the best signal integrity. High input jitter tolerance of the reclocker improves timing margin. The reclocker has a built-in loop filter, and operates without the need of a precision input reference clock. A non-disruptive eye monitor allows real time measurement of the serial data to simplify system debug and accelerate board bring-up.
The integrated 2:1 Mux and 1:2 Fanout provide flexibility for multiple video signals. The output drivers offer programmable de-emphasis to compensate board trace losses at its outputs. The integrated return loss network meets stringent SMPTE specifications across all data rates. The typical power consumption of LMH1219 is 250 mW. In the absence of input signal, power is further reduced to 16 mW.
The LMH1219 is pin compatible to LMH1226 (12G UHD reclocker) and LMH0324 (3G adaptive cable equalizer).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMH1219 | QFN (24) | 4.00 mm × 4.00 mm |
Changes from C Revision (October 2017) to D Revision
Changes from B Revision (February 2017) to C Revision
Changes from A Revision (May 2016) to B Revision
Changes from * Revision (April 2016) to A Revision
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
High Speed Differential I/O'S | |||
IN0+ | 1 | I, Analog | Single-ended complementary inputs, 75-Ω internal termination from IN0+ or IN0- to internal common mode voltage and return loss compensation network. Requires external 4.7-µF AC coupling capacitors. IN0+ is the 75-Ω input port for the adaptive cable equalizer in SMPTE video applications. |
IN0- | 2 | I, Analog | |
IN1+ | 4 | I, Analog | Differential complementary inputs with internal 100-Ω termination. Requires external 4.7-µF AC coupling capacitors for SMPTE and 10 GbE. |
IN1- | 5 | I, Analog | |
OUT0+ | 18 | O, Analog | Differential complementary outputs with 100-Ω internal termination. Requires external 4.7-µF AC coupling capacitors. Output driver OUT0± can be disabled under user control. |
OUT0- | 17 | O, Analog | |
OUT1+ | 15 | O, Analog | Differential complementary outputs with 100-Ω internal termination. Requires external 4.7-µF AC coupling capacitors. Output driver OUT1± can be disabled under user control. |
OUT1- | 14 | O, Analog | |
Control Pins | |||
LOCK_N | 12 | O, LVCMOS, OD | LOCK_N is the reclocker lock indicator for the selected input. LOCK_N is pulled LOW when the reclocker has acquired locking condition. LOCK_N is an open drain output, 3.3 V tolerant, and requires an external 2-kΩ to 5-kΩ pull-up resistor to logic supply. LOCK_N pin can be re-configured to indicate CD_N (Carrier Detect) or INT_N (Interrupt) for IN0 or IN1 through register programming. |
IN_OUT_SEL | 8 | I, 4-LEVEL | IN_OUT_SEL selects the signal flow at input ports to output ports. See Table 2 for details. This pin setting can be overridden by register control. |
OUT_CTRL | 19 | I, 4-LEVEL | OUT_CTRL selects the signal flow from the selected IN port to OUT0± and OUT1±. It selects reclocked data, reclocked data and clock, bypassed reclocker data (equalized data to output driver), or bypassed equalizer and reclocker data. See Table 4 for details. This pin setting can be overridden by register control. |
VOD_DE | 11 | I, 4-LEVEL | VOD_DE selects the driver output amplitude and de-emphasis level for both OUT0± and OUT1±. See Table 5 for details. This pin setting can be overridden by register control. |
MODE_SEL | 6 | I, 4-LEVEL | MODE_SEL enables SPI or SMBus serial control interface. See Table 6 for details. |
Serial Control Interface (SPI Mode), MODE_SEL = F (Float) | |||
SS_N | 7 | I, LVCMOS | SS_N is the Slave Select. When SS_N is at logic Low, it enables SPI access to the LMH1219 slave device. SS_N is a LVCMOS input referenced to VDDIO. |
MISO | 20 | O, LVCMOS | MISO is the SPI control serial data output from the LMH1219 slave device. MISO is a LVCMOS output referenced to VDDIO. |
MOSI | 10 | I, LVCMOS | MOSI is used as the SPI control serial data input to the LMH1219 slave device. MOSI is LVCMOS input referenced to VDDIO. |
SCK | 21 | I, LVCMOS | SCK is the SPI serial input clock to the LMH1219 slave device. SCK is LVCMOS referenced to VDDIO. |
Serial Control Interface (SMBus MODE) , MODE_SEL = L (1 kΩ to VSS) | |||
ADDR0 | 7 | Strap, 4-LEVEL | ADDR[1:0] are SMBus address straps to select one of the 16 supported SMBus addresses. ADDR[1:0] are 4-level straps and are read into the device at power up. |
ADDR1 | 20 | Strap, 4-LEVEL | |
SDA | 10 | IO, LVCMOS, OD | SDA is the SMBus bi-directional open drain SDA data line to or from the LMH1219 slave device. SDA is an open drain IO and tolerant to 3.3 V. SDA requires an external 2-kΩ to 5-kΩ pull-up resistor to the SMBus termination voltage. |
SCL | 21 | I, LVCMOS, OD | SCL is the SMBus input clock to the LMH1219 slave device. It is driven by a LVCMOS open drain driver from the SMBus master. SCL is tolerant to 3.3 V and requires an external 2-kΩ to 5-kΩ pull up resistor to the SMBus termination voltage. |
Power | |||
VSS | 3, 9, 16 | I, Ground | Ground reference. |
VIN | 24 | I, Power | VIN is connected to an external power supply. It accepts either 2.5 V ± 5% or 1.8 V ± 5%. When VIN is powered from 2.5 V, VDD_LDO is the output of an on-chip LDO regulator. For lower power operation, both VIN and VDD_LDO should be connected to a 1.8 V supply. |
VDDIO | 22 | I, Power | VDDIO powers the LVCMOS IO and 4-level input logic and connects to 2.5 V ± 5%. |
VDD_LDO | 23 | IO, Power | VDD_LDO is the output of the internal 1.8 V LDO regulator when VIN is connected to a 2.5 V supply. VDD_LDO output requires external 1-µF and 0.1-µF bypass capacitors to VSS. The internal LDO is designed to power internal circuitry only. VDD_LDO is an input when VIN is powered from 1.8 V for lower power operation. When VIN is connected to a 1.8 V supply, both VIN and VDD_LDO should be connected to a 1.8 V supply. |
VDD_CDR | 13 | I, Power | VDD_CDR powers the reclocker circuitry and connects to 2.5 V ± 5% supply. |
EP | I, Ground | EP is the exposed pad at the bottom of the QFN package. The exposed pad must be connected to the ground plane through a via array. See Figure 41 for details. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Supply Voltage for 2.5 V Mode (VDD_CDR, VIN, VDDIO) | –0.5 | 2.75 | V | ||
Supply Voltage for 1.8 V Mode (VIN, VDD_LDO) | –0.5 | 2.0 | V | ||
4-Level Input/Output Voltage (IN_OUT_SEL, OUT_CTRL, VOD_DE, MODE_SEL, ADDR0, ADDR1) | –0.5 | 2.75 | V | ||
SMBus Input/Output Voltage (SDA, SCL) | –0.5 | 4.0 | V | ||
SPI Input/Output Voltage (SS_N, MISO, MOSI, and SCK) | –0.5 | 2.75 | V | ||
Input Voltage (IN0±, IN1±) | –0.5 | 2.75 | V | ||
Input Current (IN0±, IN1±) | –30 | 30 | mA | ||
Junction Temperature | 125 | °C | |||
Storage temperature | -65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
Single Supply Mode(1) | VIN, VDDIO, VDD_CDR to VSS | 2.375 | 2.5 | 2.625 | V | |
Dual Supply Mode(2)(3) | VIN, VDD_LDO to VSS | 1.71 | 1.8 | 1.89 | V | |
VDD_CDR, VDDIO to VSS | 2.375 | 2.5 | 2.625 | |||
VDDSMBUS | SMBus: SDA, SCL Open Drain Termination Voltage | 2.375 | 3.6 | V | ||
VIN0_LAUNCH | Source Launch Amplitude before coaxial cable | Normal mode | 0.72 | 0.8 | 0.88 | Vp-p |
Splitter mode | 0.36 | 0.4 | 0.44 | |||
VIN1_LAUNCH | Source Differential Launch Amplitude | before 5-inch board trace | 300 | 850 | mVp-p | |
before 20-inch board trace | 650 | 1000 | ||||
TJUNCTION | Operating Junction Temperature | 100 | °C | |||
TAMBIENT | Ambient Temperature | –40 | 25 | 85 | °C | |
NTpsmax(4) | Maximum Supply Noise Tolerance | 50 Hz to 1 MHz, sinusoidal | <20 | mVp-p | ||
1.1 MHz to 6 GHz, sinusoidal | <10 |
THERMAL METRIC(1)(2) | LMH1219 | UNIT | |
---|---|---|---|
RTW (QFN) | |||
24 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 33.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 28.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 11.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 11.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.2 | °C/W |
PARAMETER | CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER | ||||||
PDDUAL | Power Dissipation, Dual Supply Mode | Measured with PRBS-10, Locked to 11.88 Gbps at IN0+, VOD = default, only OUT0 enabled | 250 | mW | ||
PDZ_DUAL | Power Dissipation, Dual Supply Mode | Power Save Mode, no input signal | 16 | mW | ||
PDSINGLE | Power Dissipation, Single Supply Mode | Measured with PRBS-10, Locked to 11.88 Gbps at IN0+, VOD = default, only OUT0 enabled | 290 | mW | ||
PDZ_SINGLE | Power Dissipation, Single Supply Mode | Power Save Mode, no input signal | 27 | mW | ||
IDDDUAL | Current Consumption, Dual Supply Mode | Measured at 2.5 V supply with PRBS-10, Locked to 11.88 Gbps at IN0+, VOD = Default, only OUT0 enabled | 64 | 70 | mA | |
Measured at 1.8 V supply with PRBS-10, Locked to 11.88 Gbps at IN0+, VOD = Default, only OUT0 enabled | 50 | 62 | ||||
IDDZ_DUAL | Current Consumption, Dual Supply Mode | Forced Power Save Mode, MODE_SEL = LEVEL-H, Measured at 2.5 V supply | 4 | 5 | mA | |
Forced Power Save Mode, MODE_SEL = LEVEL-H, Measured at 1.8 V supply | 3 | 9 | ||||
IDDTRANS_DUAL | Current Consumption, Dual Supply Mode Acquiring Lock, HEO/VEO Lock Monitor Disabled | Measured at 2.5 V supply with PRBS-10, IN1±, Acquiring Lock VOD = Default, OUT0 and OUT1 enabled | 90 | 101 | mA | |
Measured at 1.8 V supply with PRBS-10, IN1±, Acquiring Lock VOD = Default, OUT0 and OUT1 enabled | 30 | 37 | ||||
VDDLDO | LDO 1.8 V Output Voltage | VIN = 2.5 V, Single Supply Mode | 1.71 | 1.8 | 1.89 | V |
LVCMOS DC SPECIFICATIONS | ||||||
VIH | High Level Input Voltage | 2-Level Input (SS_N, SCK, MOSI), VDDIO = 2.5 V | 0.7 × VDDIO | VDDIO + 0.3 | V | |
2-Level Input (SCL, SDA), VDDIO = 2.5 V | 0.7 × VDDIO | 3.6 | ||||
VIL | Low Level Input Voltage | 2-Level Input (SS_N, SCK, MOSI), VDDIO = 2.5 V | -0.3 | 0.3 × VDDIO | V | |
2-Level Input (SCL, SDA), VDDIO = 2.5 V | 0 | 0.3 × VDDIO | ||||
VOH | High Level Output Voltage | IOH = –2 mA, (MISO), VDDIO = 2.5 V | 0.8 × VDDIO | VDDIO | V | |
VOL | Low Level Output Voltage | IOL = 2 mA, (MISO), VDDIO = 2.5 V | 0 | 0.2 × VDDIO | V | |
IOL = 3 mA, (LOCK_N, SCL, SDA), VDDIO = 2.5 V | 0.4 | |||||
IIH | Input High Leakage Current | SPI Mode: LVCMOS (SS_N, SCK, MOSI), Vinput = VDDIO | 15 | µA | ||
SMBus Mode: LVCMOS (LOCK_N, SCL, SDA), Vinput = VDDIO | 10 | |||||
IIL | Input Low Leakage Current | SPI Mode: LVCMOS (SS_N), Vinput = VSS | -40 | µA | ||
SPI Mode: LVCMOS (SCK, MOSI), Vinput = VSS | -15 | |||||
SMBus Mode: LVCMOS (LOCK_N, SCL, SDA), Vinput = VSS | -10 | |||||
4-LEVEL LOGIC DC SPECIFICATIONS (REFERENCE TO VDDIO, APPLY TO ALL 4-LEVEL INPUT CONTROL PINS) | ||||||
V4_LVL_H | LEVEL-H Input Voltage | Pull-up 1 kΩ to VDDIO | VDDIO | V | ||
V4_LVL_F | LEVEL-F Default Voltage | Float, VDDIO = 2.5 V | 2/3 × VDDIO | V | ||
V4_LVL_R | LEVEL-R Input Voltage | External Pull-down 20 kΩ to VSS, VDDIO = 2.5 V | 1/3 × VDDIO | V | ||
V4_LVL_L | LEVEL-L Input Voltage | External Pull-down 1 kΩ to VSS | 0 | V | ||
I4_LVL_IH | Input High Leakage Current | 4-Levels (IN_OUT_SEL, OUT_CTRL, VOD_DE, MODE_SEL), Vinput = VDDIO | 20 | 45 | 80 | µA |
SMBus Mode: 4-Levels (ADDR0, ADDR1), Vinput = VDDIO | 20 | 45 | 80 | |||
I4_LVL_IL | Input Low Leakage Current | 4-Levels (IN_OUT_SEL, OUT_CTRL, VOD_DE, MODE_SEL), Vinput = VSS | -160 | -93 | -40 | µA |
SMBus Mode: 4-Levels (ADDR0, ADDR1), Vinput = VSS | -160 | -93 | -40 | |||
RECEIVER SPECIFICATIONS (IN0+) | ||||||
RIN0_TERM | DC Input Termination | IN0+ and IN0- to VSS | 63 | 75 | 87 | Ω |
RLIN0_S11 | Input Return Loss Reference to 75 Ω(1) | S11, 5 MHz to 1.485 GHz | –20 | dB | ||
S11, 1.485 GHz to 3 GHz | –18 | |||||
S11, 3 GHz to 6 GHz | –13 | |||||
S11, 6 GHz to 12 GHz | –6.5 | |||||
VIN0_CM | IN0 DC Common Mode Voltage | Input common mode voltage at IN0+ or IN0- to VSS | 1.4 | V | ||
VWANDER | Input DC Wander | SD, signal at IN0+, Input launch amplitude = 0.8 Vp-p | 100 | mVp-p | ||
HD, 3G, 6G, 12G, signal at IN0+, Input launch amplitude = 0.8 Vp-p | 50 | |||||
RECEIVER SPECIFICATIONS (IN1±) | ||||||
RIN1_TERM | DC Input Differential Termination | Measured across IN1+ to IN1- | 80 | 100 | 120 | Ω |
RLIN1_SDD11 | Input Differential Return Loss(1) | SDD11, 10 MHz - 2.8 GHz | –21 | dB | ||
SDD11, 2.8 GHz - 6 GHz | –17 | |||||
SDD11, 6 GHz - 11.1 GHz | –8 | |||||
RLIN1_SCD11 | Differential to Common Mode Conversion(1) | SCD11, 10 MHz to 11.1 GHz | –23 | dB | ||
VIN1_CM_TOL | Input AC Common Mode Voltage Tolerance | 15 | mV (rms) | |||
VIN1_CM | IN1 DC Common Mode Voltage | Input common mode voltage at IN1+ or IN1- to VSS | 2.06 | V | ||
CDON_IN1 | CD_N = LOW, Carrier Detect (Default) Assert ON Threshold Level for input voltage | 10.3125 Gbps, 1010 Clock Pattern | 39 | mVp-p | ||
10.3125 Gbps, PRBS-31 Pattern | 25 | |||||
11.88 Gbps, EQ and PLL Pathological Pattern | 20 | |||||
CDOFF_IN1 | CD_N = HIGH, Carrier Detect (Default) De-Assert OFF Threshold Level | 10.3125 Gbps, 1010 Clock Pattern | 15 | mVp-p | ||
10.3125 Gbps, PRBS-31 Pattern | 15 | |||||
11.88 Gbps, EQ and PLL Pathological Pattern | 18 | |||||
TRANSMITTER OUTPUT (OUT0± AND OUT1±) | ||||||
VOD | Output Differential Voltage(6) | 8T pattern, VOD_DE = LEVEL-H, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE |
410 | mVp-p | ||
8T pattern, VOD_DE = LEVEL-F, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE |
485 | 560 | 620 | |||
8T pattern, VOD_DE = LEVEL-R, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE |
635 | |||||
8T pattern, VOD_DE = LEVEL-L, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE |
810 | |||||
VODDE | De-emphasized Output Differential Voltage(6) | 8T pattern, VOD_DE = LEVEL-H, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE |
410 | mVp-p | ||
8T pattern, VOD_DE = LEVEL-F, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE |
500 | |||||
8T pattern, VOD_DE = LEVEL-R, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE |
480 | |||||
8T pattern, VOD_DE = LEVEL-L, see Figure 13
SD, HD, 3G, 6G, 12G, and 10 GbE |
480 | |||||
ROUT_TERM | DC Output Differential Termination | Measured across OUTn+ and OUTn- | 80 | 100 | 120 | Ω |
tR/tF | Output Rise/Fall Time (2) | 20% - 80% using 8T Pattern SD, HD, 3G, 6G, 12G and 10 GbE, measured after 1 inch trace | 45 | ps | ||
RLTX-SDD22 | Output Differential Return Loss Measured with the Device Powered Up and Outputs a 10-MHz Clock Signal (2) | SDD22, 10 MHz - 2.8 GHz | -17 | dB | ||
SDD22, 2.8 GHz - 6 GHz | -15 | |||||
SDD22, 6 GHz - 11.1 GHz | -15 | |||||
RLTX-SCC22 | Output Common Mode Return Loss Measured with the Device Powered Up and Outputs a 10-MHz Clock Signal (2) | SCC22, 10 MHz - 4.75 GHz | -12 | dB | ||
SCC22, 4.75 GHz - 11.1 GHz | –12 | |||||
VTX_CM | AC Common Mode Voltage (2) | Default Setting, PRBS-31, 10.3125 Gbps | 5 | mV (rms) | ||
OUTPUT JITTER | ||||||
TJ | Total Jitter (BER≤1e-12), Reclocked Output (5) | 11.88 Gbps, PRBS-10, TX launch amplitude = 720 mV, 75 m Belden 1694A at IN0+ | 0.11 | 0.15 | UI | |
5.94 Gbps, PRBS-10, TX launch amplitude = 720 mV, 120 m Belden 1694A at IN0+ | 0.106 | UI | ||||
2.97 Gbps, PRBS-10, TX launch amplitude = 720 mV, 200 m Belden 1694A at IN0+ | 0.075 | UI | ||||
1.485 Gbps, PRBS-10, TX launch amplitude = 720 mV, 300 m Belden 1694A at IN0+ | 0.07 | UI | ||||
270 Mbps, PRBS-10, TX launch amplitude = 720 mV, 600 m Belden 1694A at IN0+ | 0.07 | UI | ||||
10.3125 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± | 0.09 | 0.15 | UI | |||
RJ | Random Jitter, Reclocked Output | 11.88 Gbps, PRBS-10, TX launch amplitude = 720 mV, 75 m Belden 1694A at IN0+ | 5.7 | mUI (rms) | ||
10.3125 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± | 4.1 | mUI (rms) | ||||
DJ | Deterministic Jitter, Reclocked Output | 11.88 Gbps, PRBS-10, TX launch amplitude = 720 mV, 75 m Belden 1694A at IN0+ | 40 | mUI | ||
10.3125 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± | 34 | mUI | ||||
TJRAW | Total Jitter (BER≤1e-12), RAW (Reclocker Bypassed) | 125 Mbps, PRBS-10, TX launch amplitude = 800 mV, 600 m Belden 1694A at IN0+ | 0.17 | UI | ||
1.25 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1± | 0.17 | |||||
CLOCK AND DATA RECOVERY | ||||||
LOCKRATE | IN0+ Reclocker Lock Data Rates(3) | SMPTE 12G, /1 | 11.88 | Gbps | ||
SMPTE 12G, /1.001 | 11.868 | Gbps | ||||
SMPTE 6G, /1 | 5.94 | Gbps | ||||
SMPTE 6G, /1.001 | 5.934 | Gbps | ||||
SMPTE 3G, /1 | 2.97 | Gbps | ||||
SMPTE 3G, /1.001 | 2.967 | Gbps | ||||
SMPTE HD, /1 | 1.485 | Gbps | ||||
SMPTE HD, /1.001 | 1.4835 | Gbps | ||||
SMPTE SD, /1 | 270 | Mbps | ||||
IN1± Reclocker Lock Data Rate | 10 GbE | 10.3125 | Gbps | |||
BYPASSRATE | IN0+ Bypass Reclocker Data Rate | MADI | 125 | Mbps | ||
IN1± Bypass Reclocker Data Rate | 1 GbE | 1.25 | Gbps | |||
BWPLL | PLL Bandwidth | Measured with 0.2 UI SJ at –3 dB, 10.3125 Gbps | 8 | MHz | ||
Measured with 0.2 UI SJ at –3 dB, 11.88 Gbps | 13 | |||||
Measured with 0.2 UI SJ at –3 dB, 5.94 Gbps | 7 | |||||
Measured with 0.2 UI SJ at –3 dB, 2.97 Gbps | 5 | |||||
Measured with 0.2 UI SJ at –3 dB, 1.485 Gbps | 3 | |||||
Measured with 0.2 UI SJ at –3 dB, 270 Mbps | 1 | |||||
JPEAKING | PLL Jitter Peaking | SD, HD, 3G, 6G, 12G (IN0+), and 10 GbE (IN1±) | 0.3 | dB | ||
JTOL_IN1 | IN1 Input Jitter Tolerance per SFF-8431 Appendix D.11 | Total jitter tolerance combination of Dj, Pj, and Rj at 10 GbE, with RX stress eye mask Y1, Y2 limits | >0.7 | UI | ||
JTOL_IN0 | IN0 Input Jitter Tolerance with SJ | IN0+ EQ bypassed, Sinusoidal jitter, tested at 3G, 6G and 12G; SJ amplitude low to high sweep, tested at BER ≤ 1e-12 | 0.65 | UI | ||
TLOCK | Reclocker Lock Time | All supported data rates, disable HEO/VEO monitor, IN0 EQ bypassed | 5 | ms | ||
TADAPT | EQ Adapt Time | Adaptation Time for EQ at IN0 | 5 | ms | ||
TEMPLOCK | VCO Lock with Temp Ramp | Lock Temperature Range (5°C per min, ramp up and down), –40°C to 85°C operating range, at 10.3125 Gbps and 11.88 Gbps | 125 | °C | ||
TLATENCY | Reclocker Latency(4) | Adapt mode 0, All supported data rates, disable HEO/VEO monitor, IN0 EQ bypassed | 1.5 UI + 220 | ps | ||
Adapt mode 0, All supported data rates, disable HEO/VEO monitor, IN1± EQ = default | 1.5 UI + 190 | |||||
TPD-RAW | Propagation Delay, RAW (reclocker bypassed) | All supported data rates, IN0 EQ bypassed | 300 | ps | ||
Raw Data (reclocker bypassed), IN1± EQ = default | 250 | |||||
FCLKOUT | Output Clock Frequency OUT1 Programmed to Output Recovered Clock | Operating at 11.88 Gbps | 297 | MHz | ||
Operating at 5.94 Gbps | 297 | MHz | ||||
Operating at 2.97 Gbps | 2.97 | GHz | ||||
Operating at 1.485 Gbps | 1.485 | GHz | ||||
Operating at 270 Mbps | 270 | MHz |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
FSCL | SMBus SCL Frequency | 10 | 400 | kHz | ||
TBUF | Bus Free Time Between Stop and Start Condition | 1.3 | µs | |||
THD:STA | Hold time after (Repeated) Start Condition.
After this period, the first clock is generated. |
0.6 | µs | |||
TSU:STA | Repeated Start Condition Setup Time | 0.6 | µs | |||
TSU:STO | Stop Condition Setup Time | 0.6 | µs | |||
THD:DAT | Data Hold Time | 0 | ns | |||
TSU:DAT | Data Setup Time | 100 | ns | |||
TLOW | Clock Low Period | 1.3 | µs | |||
THIGH | Clock High Period | 0.6 | µs | |||
TR | Clock/Data Rise Time | 300 | ns | |||
TF | Clock/Data Fall Time | 300 | ns |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
FSCK | SPI SCK Frequency | 10 | 20 | MHz | ||
TSCK | SCK Period | 50 | ns | |||
TPH | SCK Pulse Width High | 0.40 x TSCK | ns | |||
TPL | SCK Pulse Width Low | 0.40 x TSCK | ns | |||
TSU | MOSI Setup Time | 4 | ns | |||
TH | MOSI Hold Time | 4 | ns | |||
TSSSU | SS_N Setup Time | 14 | ns | |||
TSSH | SS_N Hold Time | 4 | ns | |||
TSSOF | SS_N Off Time | 1 | µs | |||
TODZ | MISO Driven-to-Tristate Time | 20 | ns | |||
TOZD | MISO Tristate-to-Driven Time | 10 | ns | |||
TOD | MISO Output Delay Time | 15 | ns |
The LMH1219 is a SMPTE compatible, low-power UHD adaptive cable equalizer with integrated reclocker. The LMH1219 has two inputs: a 75-Ω cable equalizer and a 100-Ω PCB (printed circuit board) equalizer. The 75-Ω cable equalizer input features an internal 75-Ω termination and compensation network for meeting stringent SMPTE return loss requirements. The 100-Ω PCB equalizer input supports high speed signals across differential PCB traces that connect to an external SFF-8431 optical module or on-board FPGA. An internal 2:1 input mux allows users to select between the 75-Ω cable equalizer and the 100-Ω PCB equalizer. The selected input then passes through a multi-rate reclocker with a built-in loop-filter. The multi-rate reclocker is compatible with SMPTE data rates (11.88, 5.94, 2.97, 1.485 Gbps, 270 Mbps) and their divide-by-1.001 sub-rates. It is also compatible with the 10 GbE data rate (10.3125 Gbps). After the reclocker, an internal 1:2 fan-out mux allows users to select the data or clock content for each output. At both outputs, the LMH1219 has 100-Ω drivers with de-emphasis. The de-emphasis feature of the drivers is designed to compensate for insertion loss caused by output PCB traces.
The operating mode of the LMH1219 can be set by 4-level control pins, SPI, or SMBus serial control interface. The LMH1219 can be powered from a single 2.5 V supply or dual 2.5 V/1.8 V supplies for lower power consumption. The LMH1219 is offered in a small 4 mm x 4 mm 24-lead QFN package.
The LMH1219 consists of several key blocks:
The 4-level input configuration pins use a resistor divider to provide four logic states for each control pin. There is an internal 30-kΩ pull-up and a 60-kΩ pull-down connected to the control pin that sets the default voltage at 2/3 x VDDIO. These resistors, together with the external resistor, combine to achieve the desired voltage level. By using the 1-kΩ pull-down, 20-kΩ pull-down, no connect, and 1-kΩ pull-up, the optimal voltage levels for each of the four input states are achieved as shown in Table 1.
LEVEL | SETTING | RESULTING PIN VOLTAGE |
---|---|---|
H | Tie 1 kΩ to VDDIO | VDDIO |
F | Float (leave pin open) | 2/3 × VDDIO |
R | Tie 20 kΩ to VSS | 1/3 × VDDIO |
L | Tie 1 kΩ to VSS | 0 |
Typical 4-Level Input Thresholds:
Both inputs of the LMH1219 have a Carrier Detect circuit to monitor the presence or absence of the input signal. When the input signal amplitude for the selected input (determined by IN_OUT_SEL pin) surpasses the Carrier Detect assert threshold, the LMH1219 operates in normal mode.
In the absence of an input signal, the LMH1219 automatically goes into Power Save Mode to conserve power consumption. When a valid signal is detected, the LMH1219 automatically exits Power Save Mode and returns to the normal operating mode.
The LMH1219 is designed to equalize data transmitted through a coaxial cable driven by a SMPTE compatible cable driver with launch amplitude of 800 mVp-p ± 10%. In applications where a 1:2 passive splitter is used, the signal amplitude is reduced by half due to the 6 dB insertion loss of the splitter. The LMH1219 is designed to support -6 dB splitter mode for IN0, enabled by SPI or SMBus serial interface. For more information, refer to the LMH1219 Register Map and the Programming Guide.
The LMH1219 has two Continuous Time Linear Equalizer (CTLE) blocks, one for each input. The CTLE compensates for frequency-dependent loss due to the transmission media prior to the device input. The CTLE accomplishes this by applying variable gain to the input signal, thereby boosting higher frequencies more than lower frequencies.
Only one CTLE is enabled at a time, in accordance with the input channel selected by the input mux. If IN0 is selected, the IN0 cable CTLE is powered on and the IN1 PCB CTLE is powered off. Alternatively, the two CTLEs can be bypassed either by using the OUT_CTRL pin or via register control.
If IN0 is selected, adaptive cable equalization is enabled by default. IN0 has an on-chip 75-Ω termination to the input common mode voltage and includes a series return loss compensation network for meeting stringent SMPTE return loss requirements. It is designed for AC coupling, requiring a 4.7-μF AC coupling capacitor for minimizing base-line wander due to the rare-occurring pathological bit pattern. The cable equalizer is designed with high gain and low noise circuitry to compensate for the insertion loss of a coaxial cable, such as Belden 1694A, which is widely used in broadcast video infrastructures.
Internal control loops are used to monitor the input signal quality and automatically select the optimum equalization boost and DC offset compensation. The LMH1219 is designed to handle the stringent pathological pattern defined in the SMPTE RP 198 and SMPTE RP 178 standards.
The IN1 PCB equalizer has an on-chip 100-Ω termination and is designed for AC coupling, requiring a 4.7-μF AC coupling capacitor for minimizing base-line wander due to the rare-occurring pathological bit pattern. The PCB equalizer can compensate up to 20 inches of board trace at data rates up to 11.88 Gbps. There are two adapt modes for IN1: AM0 manual mode and AM1 adaptive mode. In AM0 manual mode, fixed EQ boost settings are applied through user-programmable register control, whereas in AM1 adaptive mode, state machines automatically find the optimal equalization setting from a set of 16 pre-determined settings defined in Registers 0x40-0x4F.
If IN1 is selected, AM1 adaptive mode is enabled at the 10 GbE data rate by default. The PCB equalizer is able to adapt at 10.3125 Gbps (10 GbE) and 2.97 Gbps, 5.94 Gbps, and 11.88 Gbps (SMPTE) data rates. At 1.485 Gbps and 270 Mbps data rates, the equalization is fixed at 0x00 (minimum EQ boost). This fixed EQ value can be changed via register control. For more details, refer to the LMH1219 Register Map and Programming Guide.