VS = ±5 V, TA = 25°C, AV = 2V/V, RL = 100 Ω, VOUT = 2 VPP, Typical Unless Noted:
The LMH6702 is a very wideband, DC-coupled monolithic operational amplifier designed specifically for wide dynamic range systems requiring exceptional signal fidelity. Benefitting from current feedback architecture, the LMH6702 offers unity gain stability at exceptional speed without need for external compensation.
With its 720-MHz bandwidth (AV = 2 V/V, VO = 2 VPP), 10-bit distortion levels through 60-MHz (RL = 100 Ω), 1.83-nV/√Hz input referred noise and 12.5-mA supply current, the LMH6702 is the ideal driver or buffer for high-speed flash A-D and D-A converters.
Wide dynamic range systems such as radar and communication receivers that require a wideband amplifier offering exceptional signal purity will find the low input referred noise and low harmonic and intermodulation distortion of the LMH6702 an attractive high speed solution.
The LMH6702 is constructed using VIP10™ complimentary bipolar process and proven current feedback architecture. The LMH6702 is available in SOIC and SOT-23 packages.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMH6702 | SOIC (8) | 4.90 mm × 3.91 mm |
SOT-23 (5) | 2.90 mm × 1.60 mm |
Changes from G Revision (October 2014) to H Revision
Changes from F Revision (March 2013) to G Revision
Changes from E Revision (March 2013) to F Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NUMBER | |||
D | DBV | |||
-IN | 2 | 4 | I | Inverting input voltage |
+IN | 3 | 3 | I | Non-inverting input voltage |
N/C | 1, 5, 8 | – | – | No connection |
OUT | 6 | 1 | O | Output |
V- | 4 | 2 | I | Negative supply |
V+ | 7 | 5 | I | Positive supply |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VS | ±6.75 | V | ||
IOUT | See(3) | |||
Common mode input voltage | V− to V+ | V | ||
Maximum junction temperature | 150 | °C | ||
Storage temperature | −65 | 150 | °C | |
Soldering information | Infrared or convection (20 s) | 235 | °C | |
Wave soldering (10 s) | 260 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Machine Model (MM), per JEDEC specification JESD22-C101, all pins(2) | ±200 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Operating temperature | −40 | 85 | °C | ||
Nominal supply voltage | ±4 | ±6 | V |
THERMAL METRIC(1) | LMH6702 | UNIT | ||
---|---|---|---|---|
DBV (SOT-23) | D (SOIC) | |||
5 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 182 | 133 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 139 | 79 | °C/W |
RθJB | Junction-to-board thermal resistance | 40 | 73 | °C/W |
ψJT | Junction-to-top characterization parameter | 28 | 28 | °C/W |
ψJB | Junction-to-board characterization parameter | 40 | 73 | °C/W |
PARAMETER | TEST CONDITIONS | MIN(3) | TYP(4) | MAX(3) | UNIT | ||
---|---|---|---|---|---|---|---|
FREQUENCY DOMAIN PERFORMANCE | |||||||
SSBWSM | -3-dB Bandwidth | VOUT = 0.5 VPP | 1700 | MHz | |||
SSBWLG | VOUT = 2 VPP | 720 | |||||
LSBWLG | VOUT = 4 VPP | 480 | |||||
SSBWHG | VOUT = 2 VPP, AV = +10 | 140 | |||||
GF0.1dB | 0.1-dB gain flatness | VOUT = 2 VPP | 120 | MHz | |||
LPD | Linear phase deviation | DC to 100 MHz | 0.09 | deg | |||
DG | Differential gain | RL =150 Ω, 3.58 MHz | 0.024% | ||||
RL =150 Ω, 4.43 MHz | 0.021% | ||||||
DP | Differential phase | RL = 150 Ω, 3.58 MHz | 0.004 | deg | |||
RL = 150 Ω, 4.43 MHz | 0.007 | ||||||
TIME DOMAIN RESPONSE | |||||||
tR | Rise time | 2-V Step, TRS | 0.87 | ns | |||
2-V Step, TRL | 0.77 | ||||||
tF | Fall time | 6-V Step, TRS | 1.70 | ns | |||
6-V Step, TRL | 1.70 | ||||||
OS | Overshoot | 2-V Step | 0% | ||||
SR | Slew rate | 6 VPP, 40% to 60%(2) | 3100 | V/µs | |||
Ts | Settling time to 0.1% | 2-V Step | 13.4 | ns | |||
DISTORTION AND NOISE RESPONSE | |||||||
HD2L | 2nd Harmonic distortion | 2 VPP, 5 MHz(7) (SOT-23) | −100 | dBc | |||
2 VPP, 5 MHz(7) (SOIC) | −87 | ||||||
HD2 | 2VPP, 20 MHz(7) (SOT-23) | −79 | dBc | ||||
2VPP, 20 MHz(7) (SOIC) | −72 | ||||||
HD2H | 2VPP, 60 MHz(7) (SOT-23) | −63 | dBc | ||||
2VPP, 60 MHz(7) (SOIC) | −64 | ||||||
HD3L | 3rd Harmonic distortion | 2VPP, 5 MHz(7) (SOT-23) | −96 | dBc | |||
2VPP, 5 MHz(7) (SOIC) | −98 | ||||||
HD3 | 2VPP, 20 MHz(7) (SOT-23) | −88 | dBc | ||||
2VPP, 20 MHz(7) (SOIC) | −82 | ||||||
HD3H | 2VPP, 60 MHz(7) (SOT-23) | −70 | dBc | ||||
2VPP, 60 MHz(7) (SOIC) | −65 | ||||||
OIM3 | IMD | 75 MHz, PO = 10dBm/ tone | −67 | dBc | |||
VN | Input referred voltage noise | >1 MHz | 1.83 | nV/√Hz | |||
IN | Input referred inverting noise current | >1 MHz | 18.5 | pA/√Hz | |||
INN | Input referred non-inverting noise current | >1 MHz | 3.0 | pA/√Hz | |||
SNF | Total input noise floor | >1 MHz | −158 | dBm1Hz | |||
INV | Total integrated input noise | 1 MHz to 150 MHz | 35 | µV | |||
STATIC, DC PERFORMANCE | |||||||
VIO | Input offset voltage | ±1.0 | ±4.5 | mV | |||
-40 ≤ TJ ≤ 85 | ±6.0 | ||||||
DVIO | Input offset voltage average drift | See(6) | −13 | µV/°C | |||
IBN | Input bias current | Non-Inverting(5) | −6 | –15 | µA | ||
-40 ≤ TJ ≤ 85 | –21 | ||||||
DIBN | Input bias current average drift | Non-Inverting(6) | +40 | nA/°C | |||
IBI | Input bias current | Inverting(5) | −8 | ±30 | µA | ||
-40 ≤ TJ ≤ 85 | ±34 | ||||||
DIBI | Input bias current average drift | Inverting(6) | −10 | nA/°C | |||
PSRR | Power supply rejection ratio | DC | 47 | 52 | dB | ||
-40 ≤ TJ ≤ 85 | 45 | ||||||
CMRR | Common mode rejection ration | DC | 45 | 48 | dB | ||
-40 ≤ TJ ≤ 85 | 44 | ||||||
ICC | Supply current | RL = ∞ | 11.0 | 12.5 | 16.1 | mA | |
-40 ≤ TJ ≤ 85 | 10.0 | 17.5 | |||||
MISCELLANEOUS PERFORMANCE | |||||||
RIN | Input resistance | Non-Inverting | 1.4 | MΩ | |||
CIN | Input capacitance | Non-Inverting | 1.6 | pF | |||
ROUT | Output resistance | Closed Loop | 30 | mΩ | |||
VOL | Output voltage range | RL = 100 Ω | ±3.3 | ±3.5 | V | ||
-40 ≤ TJ ≤ 85 | ±3.2 | ||||||
CMIR | Input voltage range | Common Mode | ±1.9 | ±2.2 | V | ||
IO | Output current | 50 | 80 | mA |
V0 = 2 Vpp | RL = 100 Ω | RF = 237 Ω |
VOUT = 0.5 VPP | AV = 2 | RF = 232 Ω |
AV = 4 | VO = 2 VPP | RF = 237 Ω |
AV = 2 | VOUT = 6 VPP | RL = 100 Ω |
2 VPP | AV = 2 | RF = 237 Ω |
AV = -1 | RL = 1 kΩ | |
AV = 2 | RF = 237 Ω | RL = 100 Ω |
VS = ±5 V | RL = 100 Ω | |
RF = 237 Ω | RL = 150 Ω | |
VOUT = 2 VPP | RF = 237 Ω | RL = 100 Ω |
AV = 2 | VO = 2 VPP | RF = 237 Ω |
VO = 2 VPP | RL = 100 Ω | |
RL = 100 Ω | ||
AV = 2 | RL = 100 Ω | RF = 237 Ω |
AV = 2 | RF = 237 Ω | RL = 100 Ω |
VS = ±5 V | RL = 100 Ω | |
RF = 237 Ω | RL = 150 Ω | |
The LMH6702 has been optimized for exceptionally low harmonic distortion while driving very demanding resistive or capacitive loads. Generally, when used as the input amplifier to very high speed flash ADCs, the distortions introduced by the converter will dominate over the low LMH6702 distortions shown in Typical Characteristics.
The capacitor CSS, shown across the supplies in Figure 24 and Figure 25, is critical to achieving the lowest 2nd harmonic distortion. For absolute minimum distortion levels, it is also advisable to keep the supply decoupling currents (ground connections to CPOS, and CNEG in Figure 24 and Figure 25) separate from the ground connections to sensitive input circuitry (such as RG, RT, and RIN ground connections). Splitting the ground plane in this fashion and separately routing the high frequency current spikes on the decoupling caps back to the power supply (similar to Star Connection layout technique) ensures minimum coupling back to the input circuitry and results in best harmonic distortion response (especially 2nd order distortion).
If this layout technique has not been observed on a particular application board, designer may actually find that supply decoupling caps could adversely affect HD2 performance by increasing the coupling phenomenon already mentioned. Figure 22 shows actual HD2 data on a board where the ground plane is shared between the supply decoupling capacitors and the rest of the circuit. Once these capacitors are removed, the HD2 distortion levels reduce significantly, especially between 10 MHz to 20 MHz, as shown in Figure 22:
At these extremely low distortion levels, the high frequency behavior of decoupling capacitors themselves could be significant. In general, lower value decoupling caps tend to have higher resonance frequencies making them more effective for higher frequency regions. A particular application board which has been laid out correctly with ground returns split to minimize coupling, would benefit the most by having low value and higher value capacitors paralleled to take advantage of the effective bandwidth of each and extend low distortion frequency range.
Another important variable in getting the highest fidelity signal from the LMH6702 is the package itself. As already noted, coupling between high frequency current transients on supply lines and the device input can lead to excess harmonic distortion. An important source of this coupling is in fact through the device bonding wires. A smaller package, in general, will have shorter bonding wires and therefore lower coupling. This is true in the case of the SOT-23 compared to the SOIC package where a marked improvement in HD can be measured in the SOT-23 package. Figure 23 shows the HD comparing SOT-23 to SOIC package:
The LMH6702 data sheet shows both SOT-23 and SOIC data in Electrical Characteristics to aid in selecting the right package. Typical Characteristics shows SOIC package plots only.
Figure 10 shows a relatively constant difference between the test power level and the spurious level with the difference depending on frequency. The LMH6702 does not show an intercept type performance, (where the relative spurious levels change at a 2X rate versus the test tone powers), due to an internal full power bandwidth enhancement circuit that boosts the performance as the output swing increases while dissipating negligible quiescent power under low output power conditions. This feature enhances the distortion performance and full power bandwidth to match that of much higher quiescent supply current parts.
The example in Equation 1 shows the output offset computation equation for the non-inverting configuration using the typical bias current and offset specifications for AV = 2:
Output Offset:
where
Example computation for AV = +2, RF = 237Ω, RIN = 25Ω:
A good design, however, should include a worst case calculation using min/max numbers in the data sheet tables, in order to ensure worst case operation.
Further improvement in the output offset voltage and drift is possible using the composite amplifiers described in Application Note OA--07, Current Feedback Op Amp Applications Circuit Guide (SNOA365). The two input bias currents are physically unrelated in both magnitude and polarity for the current feedback topology. It is not possible, therefore, to cancel their effects by matching the source impedance for the two inputs (as is commonly done for matched input bias current devices).
The total output noise is computed in a similar fashion to the output offset voltage. Using the input noise voltage and the two input noise currents, the output noise is developed through the same gain equations for each term but combined as the square root of the sum of squared contributing elements. See Application Note OA-12, Noise Analysis for Comlinear Amplifiers (SNOA375) for a full discussion of noise calculations for current feedback amplifiers.