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  • LMK00308 3-GHz 8-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

    • SNAS576D February   2012  – March 2016 LMK00308

      PRODUCTION DATA.  

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  • LMK00308 3-GHz 8-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
      1. 9.2.1 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VCC and VCCO Power Supplies
      2. 9.3.2 Clock Inputs
      3. 9.3.3 Clock Outputs
        1. 9.3.3.1 Reference Output
  10. 10Application and Implementation
    1. 10.1 Driving the Clock Inputs
    2. 10.2 Crystal Interface
    3. 10.3 Termination and Use of Clock Drivers
      1. 10.3.1 Termination for DC Coupled Differential Operation
      2. 10.3.2 Termination for AC Coupled Differential Operation
      3. 10.3.3 Termination for Single-Ended Operation
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Current Consumption and Power Dissipation Calculations
      1. 11.2.1 Power Dissipation Example: Worst-Case Dissipation
    3. 11.3 Power Supply Bypassing
      1. 11.3.1 Power Supply Ripple Rejection
    4. 11.4 Thermal Management
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RTA|40
Thermal pad, mechanical data (Package|Pins)
  • RTA|40
    • QFND447B
Orderable Information
  • snas576d_oa
  • snas576d_pm
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DATA SHEET

LMK00308 3-GHz 8-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

1 Features

  • 3:1 Input Multiplexer:
    • Two Universal Inputs Operate up to 3.1 GHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks
    • One Crystal Input Accepts a 10 to 40 MHz Crystal or Single-Ended Clock
  • Two Banks with 4 Differential Outputs Each:
    • LVPECL, LVDS, HCSL, or Hi-Z (Selectable Per Bank)
    • LVPECL Additive Jitter with LMK03806 Clock Source at 156.25 MHz:
      • 20 fs RMS (10 kHz to 1 MHz)
      • 51 fs RMS (12 kHz to 20 MHz)
  • High PSRR: -65 / -76 dBc (LVPECL/LVDS) at 156.25 MHz
  • LVCMOS Output with Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V ± 5%
  • Industrial Temperature Range: -40°C to +85°C
  • 40-lead WQFN (6 mm × 6 mm)

2 Applications

  • Clock Distribution and Level Translation for ADCs, DACs, Multi-Gigabit Ethernet, XAUI, Fibre Channel, SATA/SAS, SONET/SDH, CPRI, High-Frequency Backplanes
  • Switches, Routers, Line Cards, Timing Cards
  • Servers, Computing, PCI Express (PCIe 3.0)
  • Remote Radio Units and Baseband Units

3 Description

The LMK00308 is a 3-GHz, 8-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 4 differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00308 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies.

The LMK00308 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LMK00308 WQFN (40) 6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

4 Functional Block Diagram

LMK00308 30177601.gif

LVPECL Output Swing (VOD) vs. Frequency

LMK00308 30177676.gif

5 Revision History

Changes from C Revision (May 2013) to D Revision

  • Added " Ultra-Low Additive Jitter" to document titleGo
  • Added, updated, or renamed the following sections: Specifications; Detailed Description; Application and Implementation; Power Supply Recommendations; Device and Documentation Support; Mechanical, Packaging, and Ordering InformationGo
  • Changed Cin (typ) from 1 pF to 4 pF (based on updated test method) in Electrical Characteristics: Crystal InterfaceGo
  • Added “Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz” parameter with 100 MHz and 156.25 MHz Test conditions, Typical values, Max values, and footnotes in Electrical Characteristics: LVPECL Outputs Go
  • Added “Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz” parameter with 100 MHz and 156.25 MHz Test conditions, Typical values, Max values, and footnotes in Electrical Characteristics: LVDS Outputs Go
  • Added footnote for VI_SE parameter in the Electrical Characteristics table. Go
  • Added new paragraph at end of Driving the Clock InputsGo
  • Changed part number in Figure 27 and Figure 28 to "LMK00308" Go
  • Changed Cin = 4 pF (typ, based on updated test method) in Crystal Interface Go
  • Added Power Supply Sequencing Go

Changes from B Revision (February 2013) to C Revision

  • Changed Target Applications by adding additional applications to the second and third bullets, and removing High-Speed and Serial Interfaces from first bullet.Go
  • Changed VCM text to condition for VIH to VCM parameter group.Go
  • Deleted VIH min value from Electrical Characteristics table.Go
  • Deleted VIL max value from Electrical Characteristics tableGo
  • Added VI_SE parameter and spec limits with corresponding table note to Electrical Characteristics Table.Go
  • Changed third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Revised to better correspond with information in Electrical Characteristics TableGo
  • Changed bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section.Go
  • Changed Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic.Go
  • Added text to second paragraph of Termination for AC Coupled Differential Operation to explain graphic update to Differential LVDS Operation with AC Coupling to Receivers.Go
  • Changed graphic for Differential LVDS Operation, AC Coupling, No Biasing by the Receiver and updated caption.Go

6 Pin Configuration and Functions

40-Pin WQFN
Package RTA
Top View
LMK00308 30177602.gif

Pin Functions(3)

PIN TYPE DESCRIPTION
NO. NAME
DAP DAP GND Die Attach Pad. Connect to the PCB ground plane for heat dissipation.
1, 2 CLKoutA0, CLKoutA0* O Differential clock output A0. Output type set by CLKoutA_TYPE pins.
3, 6 VCCOA PWR Power supply for Bank A Output buffers. VCCOA can operate from 3.3 V or 2.5 V. The VCCOA pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1)
4, 5 CLKoutA1, CLKoutA1* O Differential clock output A1. Output type set by CLKoutA_TYPE pins.
7, 8 CLKoutA2, CLKoutA2* O Differential clock output A2. Output type set by CLKoutA_TYPE pins.
9, 10 CLKoutA3, CLKoutA3* O Differential clock output A3. Output type set by CLKoutA_TYPE pins.
11, 39 CLKoutA_TYPE0, CLKoutA_TYPE1 I Bank A output buffer type selection pins (2)
12, 35 Vcc PWR Power supply for Core and Input buffer blocks. The Vcc supply operates from 3.3 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcc pin.
13 OSCin I Input for crystal. Can also be driven by a XO, TCXO, or other external single-ended clock.
14 OSCout O Output for crystal. Leave OSCout floating if OSCin is driven by a single-ended clock.
15, 18 CLKin_SEL0, CLKin_SEL1 I Clock input selection pins (2)
16, 17 CLKin0, CLKin0* I Universal clock input 0 (differential/single-ended)
19, 32 CLKoutB_TYPE0, CLKoutB_TYPE1 I Bank B output buffer type selection pins (2)
20, 31, 40 GND GND Ground
21, 22 CLKoutB3*, CLKoutB3 O Differential clock output B3. Output type set by CLKoutB_TYPE pins.
23, 24 CLKoutB2*, CLKoutB2 O Differential clock output B2. Output type set by CLKoutB_TYPE pins.
25, 28 VCCOB PWR Power supply for Bank B Output buffers. VCCOB can operate from 3.3 V or 2.5 V. The VCCOB pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1)
26, 27 CLKoutB1*, CLKoutB1 O Differential clock output B1. Output type set by CLKoutB_TYPE pins.
29, 30 CLKoutB0*, CLKoutB0 O Differential clock output B0. Output type set by CLKoutB_TYPE pins.
33, 34 CLKin1*, CLKin1 I Universal clock input 1 (differential/single-ended)
36 REFout O LVCMOS reference output. Enable output by pulling REFout_EN pin high.
37 VCCOC PWR Power supply for REFout Output buffer. VCCOC can operate from 3.3 V or 2.5 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1)
38 REFout_EN I REFout enable input. Enable signal is internally synchronized to selected clock input. (2)
(1) The output supply voltages/pins (VCCOA, VCCOB, and VCCOC) will be referred to generally as VCCO when no distinction is needed, or when the output supply can be inferred by the output bank/type.
(2) CMOS control input with internal pull-down resistor.
(3) Any unused output pins should be left floating with minimum copper length (see note in Clock Outputs), or properly terminated if connected to a transmission line, or disabled/Hi-Z if possible. See Clock Outputs for output configuration or Termination and Use of Clock Drivers output interface and termination techniques.

 
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