Refer to the PDF data sheet for device specific package drawings
The LMK00308 is a 3-GHz, 8-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 4 differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00308 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies.
The LMK00308 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMK00308 | WQFN (40) | 6.00 mm × 6.00 mm |
Changes from C Revision (May 2013) to D Revision
Changes from B Revision (February 2013) to C Revision
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
DAP | DAP | GND | Die Attach Pad. Connect to the PCB ground plane for heat dissipation. |
1, 2 | CLKoutA0, CLKoutA0* | O | Differential clock output A0. Output type set by CLKoutA_TYPE pins. |
3, 6 | VCCOA | PWR | Power supply for Bank A Output buffers. VCCOA can operate from 3.3 V or 2.5 V. The VCCOA pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1) |
4, 5 | CLKoutA1, CLKoutA1* | O | Differential clock output A1. Output type set by CLKoutA_TYPE pins. |
7, 8 | CLKoutA2, CLKoutA2* | O | Differential clock output A2. Output type set by CLKoutA_TYPE pins. |
9, 10 | CLKoutA3, CLKoutA3* | O | Differential clock output A3. Output type set by CLKoutA_TYPE pins. |
11, 39 | CLKoutA_TYPE0, CLKoutA_TYPE1 | I | Bank A output buffer type selection pins (2) |
12, 35 | Vcc | PWR | Power supply for Core and Input buffer blocks. The Vcc supply operates from 3.3 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcc pin. |
13 | OSCin | I | Input for crystal. Can also be driven by a XO, TCXO, or other external single-ended clock. |
14 | OSCout | O | Output for crystal. Leave OSCout floating if OSCin is driven by a single-ended clock. |
15, 18 | CLKin_SEL0, CLKin_SEL1 | I | Clock input selection pins (2) |
16, 17 | CLKin0, CLKin0* | I | Universal clock input 0 (differential/single-ended) |
19, 32 | CLKoutB_TYPE0, CLKoutB_TYPE1 | I | Bank B output buffer type selection pins (2) |
20, 31, 40 | GND | GND | Ground |
21, 22 | CLKoutB3*, CLKoutB3 | O | Differential clock output B3. Output type set by CLKoutB_TYPE pins. |
23, 24 | CLKoutB2*, CLKoutB2 | O | Differential clock output B2. Output type set by CLKoutB_TYPE pins. |
25, 28 | VCCOB | PWR | Power supply for Bank B Output buffers. VCCOB can operate from 3.3 V or 2.5 V. The VCCOB pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1) |
26, 27 | CLKoutB1*, CLKoutB1 | O | Differential clock output B1. Output type set by CLKoutB_TYPE pins. |
29, 30 | CLKoutB0*, CLKoutB0 | O | Differential clock output B0. Output type set by CLKoutB_TYPE pins. |
33, 34 | CLKin1*, CLKin1 | I | Universal clock input 1 (differential/single-ended) |
36 | REFout | O | LVCMOS reference output. Enable output by pulling REFout_EN pin high. |
37 | VCCOC | PWR | Power supply for REFout Output buffer. VCCOC can operate from 3.3 V or 2.5 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1) |
38 | REFout_EN | I | REFout enable input. Enable signal is internally synchronized to selected clock input. (2) |