LMK00308 3-GHz 8-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

1 Features

• 3:1 Input Multiplexer:
  • Two Universal Inputs Operate up to 3.1 GHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks
  • One Crystal Input Accepts a 10 to 40 MHz Crystal or Single-Ended Clock
• Two Banks with 4 Differential Outputs Each:
  • LVPECL, LVDS, HCSL, or Hi-Z (Selectable Per Bank)
  • LVPECL Additive Jitter with LMK03806 Clock Source at 156.25 MHz:
    • 20 fs RMS (10 kHz to 1 MHz)
    • 51 fs RMS (12 kHz to 20 MHz)
• High PSRR: -65 / -76 dBc (LVPECL/LVDS) at 156.25 MHz
• LVCMOS Output with Synchronous Enable Input
• Pin-Controlled Configuration
• V_CC Core Supply: 3.3 V ± 5%
• 3 Independent V_CCO Output Supplies: 3.3 V/2.5 V ± 5%
• Industrial Temperature Range: -40°C to +85°C
• 40-lead WQFN (6 mm × 6 mm)

2 Applications

• Clock Distribution and Level Translation for ADCs, DACs, Multi-Gigabit Ethernet, XAUI, Fibre Channel, SATA/SAS, SONET/SDH, CPRI, High-Frequency Backplanes
• Switches, Routers, Line Cards, Timing Cards
• Servers, Computing, PCI Express (PCIe 3.0)
• Remote Radio Units and Baseband Units

3 Description

The LMK00308 is a 3-GHz, 8-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 4 differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00308 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies.

The LMK00308 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

1. For all available packages, see the orderable addendum at the end of the data sheet.

4 Functional Block Diagram

LVPECL Output Swing (V_OD) vs. Frequency

5 Revision History

Changes from C Revision (May 2013) to D Revision

• Added " Ultra-Low Additive Jitter" to document titleGo
• Added, updated, or renamed the following sections: Specifications; Detailed Description; Application and Implementation; Power Supply Recommendations; Device and Documentation Support; Mechanical, Packaging, and Ordering InformationGo
• Changed Cin (typ) from 1 pF to 4 pF (based on updated test method) in Electrical Characteristics: Crystal InterfaceGo
• Added “Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz” parameter with 100 MHz and 156.25 MHz Test conditions, Typical values, Max values, and footnotes in Electrical Characteristics: LVPECL Outputs Go
• Added “Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz” parameter with 100 MHz and 156.25 MHz Test conditions, Typical values, Max values, and footnotes in Electrical Characteristics: LVDS Outputs Go
• Added footnote for V_{I_SE} parameter in the Electrical Characteristics table. Go
• Added new paragraph at end of Driving the Clock InputsGo
• Changed part number in Figure 27 and Figure 28 to "LMK00308" Go
• Changed Cin = 4 pF (typ, based on updated test method) in Crystal Interface Go
• Added Power Supply Sequencing Go

Changes from B Revision (February 2013) to C Revision

• Changed Target Applications by adding additional applications to the second and third bullets, and removing High-Speed and Serial Interfaces from first bullet.Go
• Changed V_CM text to condition for V_IH to V_CM parameter group.Go
• Deleted V_IH min value from Electrical Characteristics table.Go
• Deleted V_IL max value from Electrical Characteristics tableGo
• Added V_{I_SE} parameter and spec limits with corresponding table note to Electrical Characteristics Table.Go
• Changed third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Revised to better correspond with information in Electrical Characteristics TableGo
• Changed bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section.Go
• Changed Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic.Go
• Added text to second paragraph of Termination for AC Coupled Differential Operation to explain graphic update to Differential LVDS Operation with AC Coupling to Receivers.Go
• Changed graphic for Differential LVDS Operation, AC Coupling, No Biasing by the Receiver and updated caption.Go