LMK00334 Four-Output Clock Buffer and Level Translator for PCIe Gen 1 to Gen 5
1 Features
- 3:1 Input multiplexer
- Two universal inputs operate up to 400 MHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks
- One crystal input accepts a 10- to 40-MHz crystal or single-ended clock
- Two banks with two differential outputs each
- HCSL, or Hi-Z (selectable)
- Additive RMS phase
jitter for PCIe Gen5 at 100 MHz:
- 15 fs RMS (typical)
- High PSRR: –72 dBc at 156.25 MHz
- LVCMOS output with synchronous enable input
- Pin-controlled configuration
- VCC core supply: 3.3 V ± 5%
- Three independent VCCO output supplies: 3.3 V, 2.5 V ± 5%
- Industrial temperature range: –40°C to +105°C
- 32-pin WQFN (5 mm × 5 mm)
3 Description
The LMK00334 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. It is capable of distributing the reference clock for ADCs, DACs, multi-gigabit ethernet, XAUI, fibre channel, SATA/SAS, SONET/SDH, CPRI, and high-frequency backplanes.
The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of two HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies.
The LMK00334 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| LMK00334 | WQFN (32) | 5.00 mm × 5.00 mm |
LMK00334 Functional Block Diagram