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  • LMK00334 Four-Output Clock Buffer and Level Translator for PCIe Gen 1 to Gen 5

    • SNAS635E December   2013  – January 2022 LMK00334

      PRODUCTION DATA  

  • CONTENTS
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  • LMK00334 Four-Output Clock Buffer and Level Translator for PCIe Gen 1 to Gen 5
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements, Propagation Delay, and Output Skew
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Crystal Power Dissipation vs. RLIM
      2. 8.3.2 Clock Inputs
      3. 8.3.3 Clock Outputs
        1. 8.3.3.1 Reference Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 VCC and VCCO Power Supplies
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Driving the Clock Inputs
        2. 9.2.1.2 Crystal Interface
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Termination and Use of Clock Drivers
        2. 9.2.2.2 Termination for DC-Coupled Differential Operation
        3. 9.2.2.3 Termination for AC-Coupled Differential Operation
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Current Consumption and Power Dissipation Calculations
      1. 10.1.1 Power Dissipation Example: Worst-Case Dissipation
    2. 10.2 Power Supply Bypassing
      1. 10.2.1 Power Supply Ripple Rejection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Management
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RTV|32
    • MPQF166B
Thermal pad, mechanical data (Package|Pins)
  • RTV|32
    • QFND448B
Orderable Information
  • snas635e_oa
  • snas635e_pm
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DATA SHEET

LMK00334 Four-Output Clock Buffer and Level Translator for PCIe Gen 1 to Gen 5

1 Features

  • 3:1 Input multiplexer
    • Two universal inputs operate up to 400 MHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks
    • One crystal input accepts a 10- to 40-MHz crystal or single-ended clock
  • Two banks with two differential outputs each
    • HCSL, or Hi-Z (selectable)
    • Additive RMS phase jitter for PCIe Gen5 at 100 MHz:
      • 15 fs RMS (typical)
  • High PSRR: –72 dBc at 156.25 MHz
  • LVCMOS output with synchronous enable input
  • Pin-controlled configuration
  • VCC core supply: 3.3 V ± 5%
  • Three independent VCCO output supplies: 3.3 V, 2.5 V ± 5%
  • Industrial temperature range: –40°C to +105°C
  • 32-pin WQFN (5 mm × 5 mm)

2 Applications

  • Data center switches
  • Core routers
  • Servers, computing, PCIe Gen 3.0 to 5.0
  • Remote radio units and baseband units

3 Description

The LMK00334 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. It is capable of distributing the reference clock for ADCs, DACs, multi-gigabit ethernet, XAUI, fibre channel, SATA/SAS, SONET/SDH, CPRI, and high-frequency backplanes.

The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of two HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies.

The LMK00334 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

Device Information(1)
PART NUMBERPACKAGEBODY SIZE (NOM)
LMK00334WQFN (32)5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-6CB5C03A-3A34-4866-9217-CF4B09294208-low.gifLMK00334 Functional Block Diagram

4 Revision History

Changes from Revision D (July 2021) to Revision E (January 2022)

  • Changed data sheet titleGo
  • Added links to the Applications sectionGo
  • Added text to the Description sectionGo
  • Added example board layout to Packaging Information section.Go

Changes from Revision C (July 2017) to Revision D (July 2021)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Added PCIe Gen 5.0 to the data sheetGo
  • Corrected PN in Figure 9-4 and Figure 9-5 to LMK00334.Go

Changes from Revision B (May 2017) to Revision C (July 2017)

  • Added PCIe 4.0 compliance dataGo

Changes from Revision A (October 2014) to Revision B (May 2017)

  • Changed CLKout_EN pin to CLKout_EN throughout the data sheetGo
  • Add pins 28 and 32 to the Pin Functions table Go
  • Moved the storage temperature to the Absolute Maximum Ratings tableGo
  • Added test conditions to the output supply voltage parameter in the Recommended Operating Conditions tableGo

Changes from Revision * (December 2013) to Revision A (October 2014)

  • Added, updated, or renamed the following sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information Go
  • Changed from 1 MHz to 12 kHz in Electrical Characteristics Go
  • Deleted "The additive jitter The additive RMS jitter was approximated ... "Go

5 Pin Configuration and Functions

GUID-6B40FA7E-EFE4-49C5-ACFA-902F186C756D-low.gifFigure 5-1 RTV Package32-Pin WQFNTop View
Table 5-1 Pin Functions(3)
PIN I/O DESCRIPTION
NAME NO.
DAP DAP GND Die Attach Pad. Connect to the PCB ground plane for heat dissipation.
CLKin_SEL0 13 I Clock input selection pins (2)
CLKin_SEL1 16 I Clock input selection pins (2)
CLKin0 14 I Universal clock input 0 (differential/single-ended)
CLKin0* 15 I Universal clock input 0 (differential/single-ended)
CLKin1 27 I Universal clock input 1 (differential/single-ended)
CLKin1* 26 I Universal clock input 1 (differential/single-ended)
CLKout_EN 9 I Bank A and Bank B low active output buffer enable. (2)
CLKoutA0 3 O Differential clock output A0.
CLKoutA0* 4 O Differential clock output A0.
CLKoutA1 6 O Differential clock output A1.
CLKoutA1* 7 O Differential clock output A1.
CLKoutB1 19 O Differential clock output B1.
CLKoutB1* 18 O Differential clock output B1.
CLKoutB0 22 O Differential clock output B0.
CLKoutB0* 21 O Differential clock output B0.
GND 1, 8 17, 24 GND Ground
NC 25 — Not connected internally. Pin may be floated, grounded, or otherwise tied to any potential within the Supply Voltage range stated in the Section 6.1.
OSCin 11 I Input for crystal. Can also be driven by a XO, TCXO, or other external single-ended clock.
OSCout 12 O Output for crystal. Leave OSCout floating if OSCin is driven by a single-ended clock.
REFout 29 O LVCMOS reference output. Enable output by pulling REFout_EN pin high.
REFout_EN 31 I REFout enable input. Enable signal is internally synchronized to selected clock input. (2)
VCC 10, 28, 32 PWR Power supply for Core and Input Buffer blocks. The VCC supply operates from 3.3 V. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCC pin.
VCCOA 2, 5 PWR Power supply for Bank A Output buffers. VCCOA operates from 3.3 V or 2.5 V. The VCCOA pins are internally tied together. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCCO pin. (1)
VCCOB 20, 23 PWR Power supply for Bank B Output buffers. VCCOB operates from 3.3 V or 2.5 V. The VCCOB pins are internally tied together. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCCO pin. (1)
VCCOC 30 PWR Power supply for REFout buffer. VCCOC operates from 3.3 V or 2.5 V. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCCO pin. (1)
(1) The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the output supply can be inferred from the output bank/type.
(2) CMOS control input with internal pulldown resistor.
(3) Any unused output pins should be left floating with minimum copper length (see note in Section 8.3.3), or properly terminated if connected to a transmission line, or disabled/Hi-Z if possible. See Section 8.3.3 for output configuration and Section 9.2.2.1 for output interface and termination techniques.

 
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