The LMK00334 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. It is capable of distributing the reference clock for ADCs, DACs, multi-gigabit ethernet, XAUI, fibre channel, SATA/SAS, SONET/SDH, CPRI, and high-frequency backplanes.
The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of two HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies.
The LMK00334 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMK00334 | WQFN (32) | 5.00 mm × 5.00 mm |
Changes from Revision D (July 2021) to Revision E (January 2022)
Changes from Revision C (July 2017) to Revision D (July 2021)
Changes from Revision B (May 2017) to Revision C (July 2017)
Changes from Revision A (October 2014) to Revision B (May 2017)
Changes from Revision * (December 2013) to Revision A (October 2014)
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
DAP | DAP | GND | Die Attach Pad. Connect to the PCB ground plane for heat dissipation. |
CLKin_SEL0 | 13 | I | Clock input selection pins (2) |
CLKin_SEL1 | 16 | I | Clock input selection pins (2) |
CLKin0 | 14 | I | Universal clock input 0 (differential/single-ended) |
CLKin0* | 15 | I | Universal clock input 0 (differential/single-ended) |
CLKin1 | 27 | I | Universal clock input 1 (differential/single-ended) |
CLKin1* | 26 | I | Universal clock input 1 (differential/single-ended) |
CLKout_EN | 9 | I | Bank A and Bank B low active output buffer enable. (2) |
CLKoutA0 | 3 | O | Differential clock output A0. |
CLKoutA0* | 4 | O | Differential clock output A0. |
CLKoutA1 | 6 | O | Differential clock output A1. |
CLKoutA1* | 7 | O | Differential clock output A1. |
CLKoutB1 | 19 | O | Differential clock output B1. |
CLKoutB1* | 18 | O | Differential clock output B1. |
CLKoutB0 | 22 | O | Differential clock output B0. |
CLKoutB0* | 21 | O | Differential clock output B0. |
GND | 1, 8 17, 24 | GND | Ground |
NC | 25 | — | Not connected internally. Pin may be floated, grounded, or otherwise tied to any potential within the Supply Voltage range stated in the Section 6.1. |
OSCin | 11 | I | Input for crystal. Can also be driven by a XO, TCXO, or other external single-ended clock. |
OSCout | 12 | O | Output for crystal. Leave OSCout floating if OSCin is driven by a single-ended clock. |
REFout | 29 | O | LVCMOS reference output. Enable output by pulling REFout_EN pin high. |
REFout_EN | 31 | I | REFout enable input. Enable signal is internally synchronized to selected clock input. (2) |
VCC | 10, 28, 32 | PWR | Power supply for Core and Input Buffer blocks. The VCC supply operates from 3.3 V. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCC pin. |
VCCOA | 2, 5 | PWR | Power supply for Bank A Output buffers. VCCOA operates from 3.3 V or 2.5 V. The VCCOA pins are internally tied together. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCCO pin. (1) |
VCCOB | 20, 23 | PWR | Power supply for Bank B Output buffers. VCCOB operates from 3.3 V or 2.5 V. The VCCOB pins are internally tied together. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCCO pin. (1) |
VCCOC | 30 | PWR | Power supply for REFout buffer. VCCOC operates from 3.3 V or 2.5 V. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCCO pin. (1) |