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  • LMK04906 Ultralow Noise Clock Jitter Cleaner and Multiplier With 6 Programmable Outputs

    • SNAS589F June   2012  – August 2017 LMK04906

      PRODUCTION DATA.  

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  • LMK04906 Ultralow Noise Clock Jitter Cleaner and Multiplier With 6 Programmable Outputs
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Charge Pump Current Specification Definitions
      1. 7.1.1 Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage
      2. 7.1.2 Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch
      3. 7.1.3 Charge Pump Output Current Magnitude Variation vs Temperature
    2. 7.2 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1  System Architecture
      2. 8.1.2  PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)
      3. 8.1.3  PLL1 Tunable Crystal Support
      4. 8.1.4  VCXO/Crystal Buffered Outputs
      5. 8.1.5  Frequency Holdover
      6. 8.1.6  Integrated Loop Filter Poles
      7. 8.1.7  Internal VCO
      8. 8.1.8  External VCO Mode
      9. 8.1.9  Clock Distribution
        1. 8.1.9.1 CLKout DIVIDER
        2. 8.1.9.2 CLKout Delay
        3. 8.1.9.3 Programmable Output Type
        4. 8.1.9.4 Clock Output Synchronization
      10. 8.1.10 0-Delay
      11. 8.1.11 Default Start-Up Clocks
      12. 8.1.12 Status Pins
      13. 8.1.13 Register Readback
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Serial MICROWIRE Timing Diagram
      2. 8.3.2  Advanced MICROWIRE Timing Diagrams
        1. 8.3.2.1 Three Extra Clocks or Double Program
        2. 8.3.2.2 Three Extra Clocks With LEuWire High
        3. 8.3.2.3 Readback
      3. 8.3.3  Inputs / Outputs
        1. 8.3.3.1 PLL1 Reference Inputs (CLKin0, CLKin1, and CLKin2)
        2. 8.3.3.2 PLL2 OSCin / OSCin* Port
        3. 8.3.3.3 Crystal Oscillator
      4. 8.3.4  Input Clock Switching
        1. 8.3.4.1 Input Clock Switching - Manual Mode
        2. 8.3.4.2 Input Clock Switching - Pin Select Mode
          1. 8.3.4.2.1 Pin Select Mode and Host
          2. 8.3.4.2.2 Switch Event Without Holdover
          3. 8.3.4.2.3 Switch Event With Holdover
        3. 8.3.4.3 Input Clock Switching - Automatic Mode
          1. 8.3.4.3.1 Starting Active Clock
          2. 8.3.4.3.2 Clock Switch Event: PLL1 DLD
          3. 8.3.4.3.3 Clock Switch Event: PLL1 Vtune Rail
          4. 8.3.4.3.4 Clock Switch Event With Holdover
          5. 8.3.4.3.5 Clock Switch Event Without Holdover
        4. 8.3.4.4 Input Clock Switching - Automatic Mode With Pin Select
          1. 8.3.4.4.1 Starting Active Clock
          2. 8.3.4.4.2 Clock Switch Event: PLL1 DLD
          3. 8.3.4.4.3 Clock Switch Event: PLL1 Vtune Rail
          4. 8.3.4.4.4 Clock Switch Event With Holdover
      5. 8.3.5  Holdover Mode
        1. 8.3.5.1 Enable Holdover
        2. 8.3.5.2 Entering Holdover
        3. 8.3.5.3 During Holdover
        4. 8.3.5.4 Exiting Holdover
        5. 8.3.5.5 Holdover Frequency Accuracy and DAC Performance
        6. 8.3.5.6 Holdover Mode - Automatic Exit of Holdover
      6. 8.3.6  PLLs
        1. 8.3.6.1 PLL1
        2. 8.3.6.2 PLL2
          1. 8.3.6.2.1 PLL2 Frequency Doubler
        3. 8.3.6.3 Digital Lock Detect
      7. 8.3.7  Status PINS
        1. 8.3.7.1 Logic Low
        2. 8.3.7.2 Digital Lock Detect
        3. 8.3.7.3 Holdover Status
        4. 8.3.7.4 DAC
        5. 8.3.7.5 PLL Divider Outputs
        6. 8.3.7.6 CLKinX_LOS
        7. 8.3.7.7 CLKinX Selected
        8. 8.3.7.8 MICROWIRE Readback
      8. 8.3.8  VCO
      9. 8.3.9  Clock Distribution
        1. 8.3.9.1 Fixed Digital Delay
        2. 8.3.9.2 Fixed Digital Delay - Example
        3. 8.3.9.3 Clock Output Synchronization (SYNC)
          1. 8.3.9.3.1 Effect of SYNC
          2. 8.3.9.3.2 Methods of Generating SYNC
          3. 8.3.9.3.3 Avoiding Clock Output Interruption Due to SYNC
          4. 8.3.9.3.4 SYNC Timing
        4. 8.3.9.4 Dynamically Programming Digital Delay
          1. 8.3.9.4.1 Absolute vs Relative Dynamic Digital Delay
          2. 8.3.9.4.2 Dynamic Digital Delay and 0-Delay Mode
          3. 8.3.9.4.3 SYNC and Minimum Step Size
          4. 8.3.9.4.4 Programming Overview
          5. 8.3.9.4.5 Internal Dynamic Digital Delay Timing
          6. 8.3.9.4.6 Other Timing Requirements
        5. 8.3.9.5 Absolute Dynamic Digital Delay
          1. 8.3.9.5.1 Absolute Dynamic Digital Delay - Example
        6. 8.3.9.6 Relative Dynamic Digital Delay
          1. 8.3.9.6.1 Relative Dynamic Digital Delay - Example
      10. 8.3.10 0-Delay Mode
      11. 8.3.11 Hitless Switching
    4. 8.4 Device Functional Modes
      1. 8.4.1 Mode Selection
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Dual PLL
        2. 8.4.2.2 0-Delay Dual PLL
        3. 8.4.2.3 Single PLL
        4. 8.4.2.4 0-delay Single PLL
        5. 8.4.2.5 Clock Distribution
    5. 8.5 Programming
      1. 8.5.1 Special Programming Case for R0 to R5 for CLKoutX_DIV and CLKoutX_DDLY
        1. 8.5.1.1 Example
      2. 8.5.2 Recommended Programming Sequence
        1. 8.5.2.1 Overview
      3. 8.5.3 Readback
        1. 8.5.3.1 Readback - Example
    6. 8.6 Register Maps
      1. 8.6.1 Register Map and Readback Register Map
      2. 8.6.2 Default Device Register Settings After Power On Reset
      3. 8.6.3 Register Descriptions
        1. 8.6.3.1  Register R0 to R5
          1. 8.6.3.1.1 CLKoutX_PD, Powerdown CLKoutX Output Path
          2. 8.6.3.1.2 CLKoutX_OSCin_Sel, Clock Output Source
          3. 8.6.3.1.3 CLKoutX_ADLX_SEL[29], CLKoutX_ADLX_SEL[28], Select Analog Delay
          4. 8.6.3.1.4 CLKoutX_DDLY, Clock Channel Digital Delay
          5. 8.6.3.1.5 Reset
          6. 8.6.3.1.6 POWERDOWN
          7. 8.6.3.1.7 CLKoutX_HS, Digital Delay Half Shift
          8. 8.6.3.1.8 CLKoutX_DIV, Clock Output Divide
        2. 8.6.3.2  Registers R6 to R8
          1. 8.6.3.2.1 CLKoutX_TYPE
          2. 8.6.3.2.2 CLKoutX_ADLY
        3. 8.6.3.3  Register R10
          1. 8.6.3.3.1 OSCout0_TYPE
          2. 8.6.3.3.2 EN_OSCout0, OSCout0 Output Enable
          3. 8.6.3.3.3 OSCout0_MUX, Clock Output Mux
          4. 8.6.3.3.4 PD_OSCin, OSCin Powerdown Control
          5. 8.6.3.3.5 OSCout_DIV, Oscillator Output Divide
          6. 8.6.3.3.6 VCO_MUX
          7. 8.6.3.3.7 EN_FEEDBACK_MUX
          8. 8.6.3.3.8 VCO_DIV, VCO Divider
          9. 8.6.3.3.9 FEEDBACK_MUX
        4. 8.6.3.4  REGISTER R11
          1. 8.6.3.4.1 MODE: Device Mode
          2. 8.6.3.4.2 EN_SYNC, Enable Synchronization
          3. 8.6.3.4.3 NO_SYNC_CLKoutX
          4. 8.6.3.4.4 SYNC_CLKin2_MUX
          5. 8.6.3.4.5 SYNC_QUAL
          6. 8.6.3.4.6 SYNC_POL_INV
          7. 8.6.3.4.7 SYNC_EN_AUTO
          8. 8.6.3.4.8 SYNC_TYPE
          9. 8.6.3.4.9 EN_PLL2_XTAL
        5. 8.6.3.5  Register R12
          1. 8.6.3.5.1 LD_MUX
          2. 8.6.3.5.2 LD_TYPE
          3. 8.6.3.5.3 SYNC_PLLX_DLD
          4. 8.6.3.5.4 EN_TRACK
          5. 8.6.3.5.5 HOLDOVER_MODE
        6. 8.6.3.6  Register R13
          1. 8.6.3.6.1 HOLDOVER_MUX
          2. 8.6.3.6.2 HOLDOVER_TYPE
          3. 8.6.3.6.3 Status_CLKin1_MUX
          4. 8.6.3.6.4 Status_CLKin0_TYPE
          5. 8.6.3.6.5 DISABLE_DLD1_DET
          6. 8.6.3.6.6 Status_CLKin0_MUX
          7. 8.6.3.6.7 CLKin_SELECT_MODE
          8. 8.6.3.6.8 CLKin_Sel_INV
          9. 8.6.3.6.9 EN_CLKinX
        7. 8.6.3.7  Register 14
          1. 8.6.3.7.1 LOS_TIMEOUT
          2. 8.6.3.7.2 EN_LOS
          3. 8.6.3.7.3 Status_CLKin1_TYPE
          4. 8.6.3.7.4 CLKinX_BUF_TYPE, PLL1 CLKinX/CLKinX* Buffer Type
          5. 8.6.3.7.5 DAC_HIGH_TRIP
          6. 8.6.3.7.6 DAC_LOW_TRIP
          7. 8.6.3.7.7 EN_VTUNE_RAIL_DET
        8. 8.6.3.8  Register 15
          1. 8.6.3.8.1 MAN_DAC
          2. 8.6.3.8.2 EN_MAN_DAC
          3. 8.6.3.8.3 HOLDOVER_DLD_CNT
          4. 8.6.3.8.4 FORCE_HOLDOVER
        9. 8.6.3.9  Register 16
          1. 8.6.3.9.1 XTAL_LVL
        10. 8.6.3.10 Register 23
          1. 8.6.3.10.1 DAC_CNT
        11. 8.6.3.11 Register 24
          1. 8.6.3.11.1 PLL2_C4_LF, PLL2 Integrated Loop Filter Component
          2. 8.6.3.11.2 PLL2_C3_LF, PLL2 Integrated Loop Filter Component
          3. 8.6.3.11.3 PLL2_R4_LF, PLL2 Integrated Loop Filter Component
          4. 8.6.3.11.4 PLL2_R3_LF, PLL2 Integrated Loop Filter Component
          5. 8.6.3.11.5 PLL1_N_DLY
          6. 8.6.3.11.6 PLL1_R_DLY
          7. 8.6.3.11.7 PLL1_WND_SIZE
        12. 8.6.3.12 Register 25
          1. 8.6.3.12.1 DAC_CLK_DIV
          2. 8.6.3.12.2 PLL1_DLD_CNT
        13. 8.6.3.13 Register 26
          1. 8.6.3.13.1 PLL2_WND_SIZE
          2. 8.6.3.13.2 EN_PLL2_REF_2X, PLL2 Reference Frequency Doubler
          3. 8.6.3.13.3 PLL2_CP_POL, PLL2 Charge Pump Polarity
          4. 8.6.3.13.4 PLL2_CP_GAIN, PLL2 Charge Pump Current
          5. 8.6.3.13.5 PLL2_DLD_CNT
          6. 8.6.3.13.6 PLL2_CP_TRI, PLL2 Charge Pump TRI-STATE
        14. 8.6.3.14 Register 27
          1. 8.6.3.14.1 PLL1_CP_POL, PLL1 Charge Pump Polarity
          2. 8.6.3.14.2 PLL1_CP_GAIN, PLL1 Charge Pump Current
          3. 8.6.3.14.3 CLKinX_PreR_DIV
          4. 8.6.3.14.4 PLL1_R, PLL1 R Divider
          5. 8.6.3.14.5 PLL1_CP_TRI, PLL1 Charge Pump TRI-STATE
        15. 8.6.3.15 Register 28
          1. 8.6.3.15.1 PLL2_R, PLL2 R Divider
          2. 8.6.3.15.2 PLL1_N, PLL1 N Divider
        16. 8.6.3.16 REGISTER 29
          1. 8.6.3.16.1 OSCin_FREQ, PLL2 Oscillator Input Frequency Register
          2. 8.6.3.16.2 PLL2_FAST_PDF, High PLL2 Phase Detector Frequency
          3. 8.6.3.16.3 PLL2_N_CAL, PLL2 N Calibration Divider
        17. 8.6.3.17 Register 30
          1. 8.6.3.17.1 PLL2_P, PLL2 N Prescaler Divider
          2. 8.6.3.17.2 PLL2_N, PLL2 N Divider
        18. 8.6.3.18 Register 31
          1. 8.6.3.18.1 READBACK_LE
          2. 8.6.3.18.2 READBACK_ADDR
          3. 8.6.3.18.3 uWire_LOCK
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Loop Filter
        1. 9.1.1.1 PLL1
        2. 9.1.1.2 PLL2
      2. 9.1.2 Driving CLKin and OSCin Inputs
        1. 9.1.2.1 Driving CLKin Pins With a Differential Source
        2. 9.1.2.2 Driving CLKin Pins With a Single-Ended Source
      3. 9.1.3 Termination and Use of Clock Output (Drivers)
        1. 9.1.3.1 Termination for DC Coupled Differential Operation
        2. 9.1.3.2 Termination for AC Coupled Differential Operation
        3. 9.1.3.3 Termination for Single-Ended Operation
      4. 9.1.4 Frequency Planning With the LMK04906 Family
      5. 9.1.5 PLL Programming
        1. 9.1.5.1 Example PLL2 N Divider Programming
      6. 9.1.6 Digital Lock Detect Frequency Accuracy
        1. 9.1.6.1 Minimum Lock Time Calculation Example
      7. 9.1.7 Calculating Dynamic Digital Delay Values For Any Divide
        1. 9.1.7.1 Example
      8. 9.1.8 Optional Crystal Oscillator Implementation (OSCin/OSCin*)
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
          1. 9.2.2.1.1 Clock Architect
          2. 9.2.2.1.2 Clock Design Tool
          3. 9.2.2.1.3 Calculation Using LCM
        2. 9.2.2.2 Device Configuration
          1. 9.2.2.2.1 PLL LO Reference
          2. 9.2.2.2.2 POR Clock
        3. 9.2.2.3 PLL Loop Filter Design
          1. 9.2.2.3.1 PLL1 Loop Filter Design
          2. 9.2.2.3.2 PLL2 Loop Filter Design
        4. 9.2.2.4 Clock Output Assignment
        5. 9.2.2.5 Other Device Specific Configuration
          1. 9.2.2.5.1 Digital Lock Detect
          2. 9.2.2.5.2 Holdover
        6. 9.2.2.6 Device Programming
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 System Level Diagram
    4. 9.4 Do's and Don'ts
      1. 9.4.1 LVCMOS Complementary vs. Non-Complementary Operation
      2. 9.4.2 LVPECL Outputs
  10. 10Power Supply Recommendations
    1. 10.1 Pin Connection Recommendations
      1. 10.1.1 Vcc Pins and Decoupling
        1. 10.1.1.1 Vcc2, Vcc3, Vcc10, Vcc11, Vcc12, Vcc13 (CLKout Vccs)
        2. 10.1.1.2 Vcc1 (VCO), Vcc4 (Digital), and Vcc9 (PLL2)
        3. 10.1.1.3 Vcc6 (PLL1 Charge Pump) and Vcc8 (PLL2 Charge Pump)
        4. 10.1.1.4 Vcc5 (CLKin), Vcc7 (OSCin & OSCout0)
      2. 10.1.2 Unused Clock Outputs
      3. 10.1.3 Unused Clock Inputs
      4. 10.1.4 LDO Bypass
    2. 10.2 Current Consumption and Power Dissipation Calculations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • NKD|64
    • MPQS032B
Thermal pad, mechanical data (Package|Pins)
  • NKD|64
    • QFND765
Orderable Information
  • snas589f_oa
  • snas589f_pm
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

LMK04906 Ultralow Noise Clock Jitter Cleaner and Multiplier With 6 Programmable Outputs

1 Features

  • Ultralow RMS Jitter Performance
    • 100-fs RMS Jitter (12 kHz to 20 MHz)
    • 123-fs RMS Jitter (100 Hz to 20 MHz)
  • Dual Loop PLLatinum™ PLL Architecture
    • PLL1
      • Integrated Low-Noise Crystal Oscillator Circuit
      • Holdover Mode when Input Clocks are Lost
        • Automatic or Manual Triggering/Recovery
    • PLL2
      • Normalized [1 Hz] PLL Noise Floor of –227 dBc/Hz
      • Phase Detector Rate up to 155 MHz
      • OSCin Frequency-doubler
      • Integrated Low-Noise VCO
  • 3 Redundant Input Clocks with LOS
    • Automatic and Manual Switch-Over Modes
  • 50% Duty Cycle Output Divides, 1 to 1045 (Even and Odd)
  • LVPECL, LVDS, or LVCMOS Programmable Outputs
  • Precision Digital Delay, Fixed or Dynamically Adjustable
  • 25-ps Step Analog Delay Control.
  • 6 Differential Outputs. Up to 12 Single Ended.
    • Up to 5 VCXO/Crystal Buffered Outputs
  • Clock Rates of up to 2600 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-mode: Dual PLL, Single PLL, and Clock Distribution
  • Industrial Temperature Range: –40 to 85 °C
  • 3.15-V to 3.45-V Operation
  • Package: 64-Pin WQFN (9 mm × 9 mm × 0.8 mm)

2 Applications

  • 10G, 40G, and 100G OTN Line Cards
  • SONET/SDH OC-48/STM-16 and OC-192/STM-64 Line Cards
  • GbE/10GbE, 1/2/4/8/10GFC Line Cards
  • ITU G.709 and Custom FEC Line Cards
  • Synchronous Ethernet
  • Optical Modules
  • DSLAM/MSANs
  • Test and Measurement
  • Broadcast Video
  • Wireless Basestations
  • Data Converter Clocking
  • Microwave ODU and IDUs for Wireless Backhaul

3 Description

The LMK04906 is the industry's highest performance clock jitter attenuator with superior clock jitter cleaning, generation, and distribution with advanced features to meet high performance timing application needs.

The LMK04906 accepts 3 clock inputs ranging from 1 kHz to 500 MHz and generates 6 unique clock output frequencies ranging from 284 kHz to 2.6 GHz. The LMK04906 can also buffer a crystal or VCXO to generate a 7th unique clock frequency.

The device provides virtually all frequency translation combinations required for SONET, Ethernet, Fibre Channel and multi-mode Wireless Base Stations.

The LMK04906 input clock frequency and clock multiplication ratio are programmable through a SPI interface.

Device Information(1)

PART NUMBER VCO FREQUENCY REFERENCE INPUTS
LMK04906 2370 to 2600 MHz 3
  1. For all available packages, see the orderable addendum at the end of the data sheet.

System Application Diagram

LMK04906 30179139.gif

Simplified LMK04906 Block Diagram

LMK04906 30179140.gif

4 Revision History

Changes from E Revision (August 2016) to F Revision

  • Changed From: CLKout3_PD = 0 To: CLKout2_PD = 0 in Table 7Go
  • Changed From: CLKout3_PD = 0 To: CLKout2_PD = 0 in Table 9Go

Changes from D Revision (May 2013) to E Revision

  • Changed 750 to 500Go
  • Changed 2.26 MHz to 284 kHzGo
  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Changed Clock Switch Event With Holdover section.Go
  • Deleted Clock Switch Event without Holdover section.Go
  • Changed 5 cycles to 5.5 cyclesGo
  • Changed 5 cycles to 5.5 cyclesGo
  • Added (Auto modes only).Go
  • Changed equationGo

Changes from C Revision (May 2013) to D Revision

  • Changed layout of National Semiconductor Data Sheet to TI format.Go

5 Pin Configuration and Functions

NKD Package
64-Pin WQFN With Exposed Pad
Top View
LMK04906 30179102.gif

Pin Functions

PIN I/O TYPE DESCRIPTION(1)
NAME NO.
Vcc13 1 — PWR Power Supply for CLKou0
NC 2, 5, 7, 8, 9, 15, 17, 19
22, 47, 51, 55, 56, 60,
61, 64		 — No Connect These pins must be left floating.
CLKout0*, CLKout0 3, 4 O Programmable Clock output 0.
SYNC / Status_CLKin2 6 I/O Programmable CLKout Synchronization input or CLKin2 Status output.
Vcc1 10 — PWR Power supply for VCO LDO.
LDObyp1 11 — ANLG LDO Bypass, bypassed to ground with 10 µF capacitor.
LDObyp2 12 — ANLG LDO Bypass, bypassed to ground with a 0.1 µF capacitor.
CLKout1, CLKout1* 13, 14 O Programmable Clock output 1.
Vcc2 16 — PWR Power supply for CLKout1.
Vcc3 18 — PWR Power supply for CLKout2
CLKout2*, CLKout2 20, 21 O Programmable Clock output 2
GND 23 — PWR Ground
Vcc4 24 — PWR Power supply for digital.
CLKin1, CLKin1* 25, 26 I ANLG Reference Clock Input Port 1 for PLL1. AC or DC Coupled.
FBCLKin, FBCLKin* Feedback input for external clock feedback input (0-delay mode). AC or DC Coupled.
Fin/Fin* External VCO input (External VCO mode). AC or DC Coupled.
Status_Holdover 27 I/O Programmable Programmable status pin, default readback output. Programmable to holdover mode indicator. Other options available by programming.
CLKin0, CLKin0* 28, 29 I ANLG Reference Clock Input Port 0 for PLL1.
AC or DC Coupled.
Vcc5 30 — PWR Power supply for clock inputs.
CLKin2, CLKin2* 31, 32 I ANLG Reference Clock Input Port 2 for PLL1,
AC or DC Coupled.
Status_LD 33 I/O Programmable Programmable status pin, default lock detect for PLL1 and PLL2. Other options available by programming.
CPout1 34 O ANLG Charge pump 1 output.
Vcc6 35 — PWR Power supply for PLL1, charge pump 1.
OSCin, OSCin* 36, 37 I ANLG Feedback to PLL1, Reference input to PLL2.
AC Coupled.
Vcc7 38 — PWR Power supply for OSCin port.
OSCout0, OSCout0* 39, 40 O Programmable Buffered output 0 of OSCin port.
Vcc8 41 — PWR Power supply for PLL2, charge pump 2.
CPout2 42 O ANLG Charge pump 2 output.
Vcc9 43 — PWR Power supply for PLL2.
LEuWire 44 I CMOS MICROWIRE Latch Enable Input.
CLKuWire 45 I CMOS MICROWIRE Clock Input.
DATAuWire 46 I CMOS MICROWIRE Data Input.
Vcc10 48 — PWR Power supply for CLKout3.
CLKout3, CLKout3* 49, 50 O Programmable Clock output 3.
Vcc11 52 — PWR Power supply for CLKout4.
CLKout4, CLKout4* 53, 54 O Programmable Clock output 4.
Vcc12 57 — PWR Power supply for CLKout5.
CLKout5, CLKout5* 58, 59 O Programmable Clock output 5.
Status_CLKin0 62 I/O Programmable Programmable status pin. Default is input for pin control of PLL1 reference clock selection. CLKin0 LOS status and other options available by programming.
Status_CLKin1 63 I/O Programmable Programmable status pin. Default is input for pin control of PLL1 reference clock selection. CLKin1 LOS status and other options available by programming.
DAP DAP — GND DIE ATTACH PAD, connect to GND.
(1) See Application and Implementation section for recommended connections.

 
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