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Data Sheet
LMK5B33414 3-DPLL 3-APLL 4-IN 14-OUT
Network Synchronizer With BAW VCO for
Ethernet-Based Networking Applications
1 FeaturesUltra-low jitter BAW VCO based
Ethernet clocks
13fs typical RMS jitter at 625MHz
with 4MHz 1st order high-pass filter (HPF)
24fs typical RMS jitter at 312.5MHz
with 4MHz 1st order HPF
42fs typical/ 60fs maximum RMS jitter at 312.5MHz
47fs typical/ 65fs maximum RMS jitter
at 156.25MHz
Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog
Phase Locked Loops (APLLs)
Programmable DPLL loop bandwidth from
1mHz to 4kHz
< 1ppt DCO frequency adjustment
step size
Four
differential or single-ended DPLL inputs 14
differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formats
Up to 18
total frequency outputs when configured with 6 LVCMOS frequency outputs on
OUT[1:0]_P/N, GPIO1, and GPIO2 and 12 differential outputs on OUT[13:2]_P/N
1Hz (1PPS) to 1250MHz output frequency with programmable swing and
common mode
PCIe Gen 1 to 6 compliant
I2 C, 3-wire SPI, or 4-wire SPI –40°C to 85°C operating temperature
2 Applications
Wired networking
SyncE (G.8262), SONET/SDH
(Stratum 3/3E, G.813, GR-1244, GR-253), IEEE-1588 PTP secondary clock
Jitter cleaning, wander
attenuation, and reference clock generation for 112G/224G PAM-4 SerDes
100G-800G data center switches , core
routers , edge
routers , WLAN
Data center and enterprise computing
Smart Network Interface
Card (NIC)
Optical Transport Networks (OTN
G.709)
Broadband fixed line access
Industrial