LMK5C22212AS1 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With JESD204B/C and BAW for Wireless Communications With IEEE-1588 PTP Stack

1 Features

Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks
- 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
- 50fs typical/ 62fs maximum RMS jitter at 245.76MHz
2 high-performance Digital Phase Locked Loops (DPLLs) with 2 Analog Phase Locked Loops (APLLs)
- Programmable DPLL loop filter bandwidth from 1mHz to 4kHz
- < 1ppt DCO frequency adjustment step size
2 differential or single-ended DPLL inputs
- 1Hz (1PPS) to 800MHz input frequency
- Digital Holdover and Hitless Switching
12 differential outputs with programmable HSDS, AC-LVPECL, LVDS and HSCL formats
- Up to 16 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT0_P/N, OUT1_P/N, GPIO1 and GPIO2 and 10 differential outputs on OUT2_P/N to OUT11_P/N
- 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
- PCIe Gen 1 to 6 compliant
I²C or 3-wire/4-wire SPI

4G and 5G Wireless Networks
- Active Antenna System (AAS), mMIMO
- Macro Remote Radio Unit (RRU)
- CPRI/eCPRI Baseband, Centralized, Distributed Units (BBU, CU, DU)
- Small cell base station
SyncE (G.8262), SONET/SDH (Stratum 3/3E, G.813, GR-1244, GR-253), IEEE-1588 PTP secondary clock
Jitter cleaning, wander attenuation, and reference clock generation for 112G/224G PAM4 SerDes
Optical Transport Networks (OTN G.709)
Broadband fixed line access
Industrial
- Test and measurement